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https://github.com/openhwgroup/cvw
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85 lines
3.2 KiB
Systemverilog
85 lines
3.2 KiB
Systemverilog
///////////////////////////////////////////
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// busfsm.sv
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//
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// Written: Ross Thompson ross1728@gmail.com December 29, 2021
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// Modified:
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//
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// Purpose: Load/Store Unit's interface to BUS for cacheless system
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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// HCLK and clk must be the same clock!
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module busfsm
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(input logic HCLK,
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input logic HRESETn,
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// IEU interface
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input logic Flush,
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input logic [1:0] BusRW,
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input logic Stall,
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output logic BusCommitted,
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output logic BusStall,
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output logic CaptureEn,
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input logic HREADY,
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output logic [1:0] HTRANS,
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output logic HWRITE
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);
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typedef enum logic [2:0] {ADR_PHASE,
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DATA_PHASE,
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MEM3} busstatetype;
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typedef enum logic [1:0] {AHB_IDLE = 2'b00, AHB_BUSY = 2'b01, AHB_NONSEQ = 2'b10, AHB_SEQ = 2'b11} ahbtranstype;
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(* mark_debug = "true" *) busstatetype CurrState, NextState;
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always_ff @(posedge HCLK)
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if (~HRESETn | Flush) CurrState <= #1 ADR_PHASE;
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else CurrState <= #1 NextState;
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always_comb begin
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case(CurrState)
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ADR_PHASE: if(HREADY & |BusRW) NextState = DATA_PHASE;
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else NextState = ADR_PHASE;
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DATA_PHASE: if(HREADY) NextState = MEM3;
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else NextState = DATA_PHASE;
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MEM3: if(Stall) NextState = MEM3;
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else NextState = ADR_PHASE;
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default: NextState = ADR_PHASE;
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endcase
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end
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assign BusStall = (CurrState == ADR_PHASE & |BusRW) |
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// (CurrState == DATA_PHASE & ~BusRW[0]); // possible optimization here. fails uart test, but i'm not sure the failure is valid.
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(CurrState == DATA_PHASE);
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assign BusCommitted = CurrState != ADR_PHASE;
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assign HTRANS = (CurrState == ADR_PHASE & HREADY & |BusRW & ~Flush) ? AHB_NONSEQ : AHB_IDLE;
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assign HWRITE = BusRW[0];
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assign CaptureEn = CurrState == DATA_PHASE;
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endmodule
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