Kip Macsai-Goren bb8ec549a7 fixed issue with tlbflush remaining high during a stalled sfence instruction		2021-07-21 17:43:36 -04:00
..
csr.sv	Added performance counters for dcache access and dcache miss.	2021-07-19 22:12:20 -05:00
csrc.sv	Added performance counters for dcache access and dcache miss.	2021-07-19 22:12:20 -05:00
csri.sv	Gave names to for loops in generate blocks for ease of reference	2021-07-04 18:52:16 -04:00
csrm.sv	make testbench check the same CSRs that QEMU logs; change CLINT to reset MTIMECMP to -1 so that we don't instantly get a timer interrupt upon reset	2021-07-19 15:13:03 -04:00
csrn.sv	Gave names to for loops in generate blocks for ease of reference	2021-07-04 18:52:16 -04:00
csrs.sv	Simplified tlbmixer mux to and-or	2021-07-08 23:34:24 -04:00
csrsr.sv	Fixed writting MStatus FS bits	2021-07-13 13:20:30 -04:00
csru.sv	Fixed writting MStatus FS bits	2021-07-13 13:20:30 -04:00
privdec.sv	Implemented TSR, TW, TVM, MXR status bits	2021-07-06 01:32:05 -04:00
privileged.sv	fixed issue with tlbflush remaining high during a stalled sfence instruction	2021-07-21 17:43:36 -04:00
trap.sv	trap.sv comment cleanup	2021-07-17 16:01:07 -04:00