cvw/pipelined/src/ifu
Ross Thompson cd0da2e3b3 Updated the names of the *WriteDataM inside the LSU to more meaningful names.
Moved the FWriteDataMux so that the bus and dtim both get fpu stores.
Modified the PMA to disallow double sized reads when XLEN=32.
2022-08-23 10:34:39 -05:00
..
.ifu.sv.swp Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault. 2022-01-27 17:11:27 -06:00
bpred.sv Fixed grammar on two comments in bpred.sv 2022-05-16 22:41:18 +00:00
BTBPredictor.sv fpu compare simplification, minor cleanup 2022-03-29 17:11:28 +00:00
CodeAligner.py Renamed wally-pipelined to pipelined 2022-01-04 19:47:41 +00:00
decompress.sv Reformatted MIT license to 95 characters 2022-01-07 12:58:40 +00:00
globalHistoryPredictor.sv Reformatted MIT license to 95 characters 2022-01-07 12:58:40 +00:00
gsharePredictor.sv replaced k with bpred size 2022-04-18 04:21:03 +00:00
ifu.sv Updated the names of the *WriteDataM inside the LSU to more meaningful names. 2022-08-23 10:34:39 -05:00
localHistoryPredictor.sv Reformatted MIT license to 95 characters 2022-01-07 12:58:40 +00:00
RAsPredictor.sv Reformatted MIT license to 95 characters 2022-01-07 12:58:40 +00:00
satCounter2.sv Reformatted MIT license to 95 characters 2022-01-07 12:58:40 +00:00
spillsupport.sv Added parameter to spillsupport. 2022-03-08 16:38:48 -06:00
SRAM2P1R1W.sv bit write update 2022-03-09 19:09:20 +00:00
twoBitPredictor.sv Reformatted MIT license to 95 characters 2022-01-07 12:58:40 +00:00