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43 lines
1.6 KiB
Systemverilog
43 lines
1.6 KiB
Systemverilog
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///////////////////////////////////////////
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// cnt.sv
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//
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// Written: Kevin Kim <kekim@hmc.edu>
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// Created: 4 February 2023
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// Modified:
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//
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// Purpose: Sign/Zero Extension Submodule
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//
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// Documentation: RISC-V System on Chip Design Chapter ***
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module ext #(parameter WIDTH = 32) (
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input logic [WIDTH-1:0] A, // Operand
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output logic [WIDTH-1:0] sexthResult, // sign extend halfword result
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output logic [WIDTH-1:0] sextbResult, // sign extend byte result
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output logic [WIDTH-1:0] zexthResult); // zero extend halfword result
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assign sexthResult = {{(WIDTH-16){A[15]}},A[15:0]};
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assign zexthResult = {{(WIDTH-16){1'b0}},A[15:0]};
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assign sextbResult = {{(WIDTH-8){A[7]}},A[7:0]};
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endmodule |