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44 lines
1.5 KiB
Systemverilog
44 lines
1.5 KiB
Systemverilog
///////////////////////////////////////////
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// clmul.sv
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//
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// Written: Kevin Kim <kekim@hmc.edu>
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// Created: 1 February 2023
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// Modified:
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//
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// Purpose: Carry-Less multiplication top-level unit
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//
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// Documentation: RISC-V System on Chip Design Chapter ***
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module byteUnit #(parameter WIDTH=32) (
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input logic [WIDTH-1:0] A, // Operands
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output logic [WIDTH-1:0] OrcBResult, // OrcB result
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output logic [WIDTH-1:0] Rev8Result); // Rev8 result
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genvar i;
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for (i=0;i<WIDTH;i+=8) begin:loop
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assign OrcBResult[i+7:i] = {8{|A[i+7:i]}};
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assign Rev8Result[WIDTH-i-1:WIDTH-i-8] = A[i+7:i];
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end
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endmodule |