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218 lines
9.2 KiB
Systemverilog
218 lines
9.2 KiB
Systemverilog
///////////////////////////////////////////
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// plic.sv
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//
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// Written: bbracker@hmc.edu 18 January 2021
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// Modified:
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//
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// Purpose: Platform-Level Interrupt Controller
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// Based on RISC-V spec (https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc)
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// With clarifications from ROA's existing implementation (https://roalogic.github.io/plic/docs/AHB-Lite_PLIC_Datasheet.pdf)
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// Supports only 1 target core and only a global threshold.
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//
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// *** Big questions:
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// Do we detect requests as level-triggered or edge-trigged?
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// If edge-triggered, do we want to allow 1 source to be able to make a number of repeated requests?
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module plic (
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input logic HCLK, HRESETn,
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input logic HSELPLIC,
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input logic [27:0] HADDR, // *** could factor out entryd into HADDRd at the level of uncore
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input logic HWRITE,
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input logic HREADY,
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input logic [1:0] HTRANS,
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input logic [`XLEN-1:0] HWDATA,
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input logic UARTIntr,GPIOIntr,
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output logic [`XLEN-1:0] HREADPLIC,
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output logic HRESPPLIC, HREADYPLIC,
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output logic ExtIntM);
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localparam N=`PLIC_NUM_SRC; // should not exceed 63; does not inlcude source 0, which does not connect to anything according to spec
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logic memwrite, memread, initTrans;
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logic [23:0] entry, entryd;
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logic [31:0] Din, Dout;
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logic [N:1] requests;
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logic [2:0] intPriority[N:1];
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logic [2:0] intThreshold;
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logic [N:1] intPending, nextIntPending, intEn, intInProgress;
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logic [5:0] intClaim; // ID's are 6 bits if we stay within 63 sources
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logic [N:1] pendingArray[7:1];
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logic [7:1] pendingPGrouped;
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logic [7:1] pendingMaxP;
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logic [N:1] pendingRequestsAtMaxP;
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logic [7:1] threshMask;
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// =======
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// AHB I/O
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// =======
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assign entry = {HADDR[23:2],2'b0};
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assign initTrans = HREADY & HSELPLIC & (HTRANS != 2'b00);
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assign memread = initTrans & ~HWRITE;
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// entryd and memwrite are delayed by a cycle because AHB controller waits a cycle before outputting write data
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flopr #(1) memwriteflop(HCLK, ~HRESETn, initTrans & HWRITE, memwrite);
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flopr #(24) entrydflop(HCLK, ~HRESETn, entry, entryd);
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assign HRESPPLIC = 0; // OK
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assign HREADYPLIC = 1'b1; // PLIC never takes >1 cycle to respond
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// account for subword read/write circuitry
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// -- Note PLIC registers are 32 bits no matter what; access them with LW SW.
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if (`XLEN == 64) begin
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assign Din = entryd[2] ? HWDATA[63:32] : HWDATA[31:0];
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assign HREADPLIC = entryd[2] ? {Dout,32'b0} : {32'b0,Dout};
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end else begin // 32-bit
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assign Din = HWDATA[31:0];
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assign HREADPLIC = Dout;
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end
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// ==================
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// Register Interface
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// ==================
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always @(posedge HCLK,negedge HRESETn) begin
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// resetting
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if (~HRESETn) begin
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intPriority <= #1 '{default:3'b0};
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intEn <= #1 {N{1'b0}};
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intThreshold <= #1 3'b0;
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intInProgress <= #1 {N{1'b0}};
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// writing
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end else begin
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if (memwrite)
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casez(entryd)
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24'h0000??: intPriority[entryd[7:2]] <= #1 Din[2:0];
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`ifdef PLIC_NUM_SRC_LT_32
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24'h002000: intEn[N:1] <= #1 Din[N:1];
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`endif
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`ifndef PLIC_NUM_SRC_LT_32
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24'h002000: intEn[31:1] <= #1 Din[31:1];
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24'h002004: intEn[N:32] <= #1 Din[31:0];
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`endif
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24'h200000: intThreshold[2:0] <= #1 Din[2:0];
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24'h200004: intInProgress <= #1 intInProgress & ~(4'b1 << (Din[5:0]-1)); // lower "InProgress" to signify completion
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endcase
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// reading
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if (memread)
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casez(entry)
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24'h0000??: Dout <= #1 {29'b0,intPriority[entry[7:2]]};
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`ifdef PLIC_NUM_SRC_LT_32
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24'h001000: Dout <= #1 {{(31-N){1'b0}},intPending[N:1],1'b0};
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24'h002000: Dout <= #1 {{(31-N){1'b0}},intEn[N:1],1'b0};
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`endif
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`ifndef PLIC_NUM_SRC_LT_32
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24'h001000: Dout <= #1 {intPending[31:1],1'b0};
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24'h001004: Dout <= #1 {{(63-N){1'b0}},intPending[N:32]};
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24'h002000: Dout <= #1 {intEn[31:1],1'b0};
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24'h002004: Dout <= #1 {{(63-N){1'b0}},intEn[N:32]};
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`endif
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24'h200000: Dout <= #1 {29'b0,intThreshold[2:0]};
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24'h200004: begin
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Dout <= #1 {26'b0,intClaim};
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intInProgress <= #1 intInProgress | (4'b1 << (intClaim-1)); // claimed requests are currently in progress of being serviced until they are completed
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end
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default: Dout <= #1 32'h0; // invalid access
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endcase
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else
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Dout <= #1 32'h0;
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end
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end
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// connect sources to requests
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always_comb begin
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requests = {N{1'b0}};
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`ifdef PLIC_GPIO_ID
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requests[`PLIC_GPIO_ID] = GPIOIntr;
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`endif
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`ifdef PLIC_UART_ID
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requests[`PLIC_UART_ID] = UARTIntr;
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`endif
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end
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// pending updates
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// *** verify that this matches the expectations of the things that make requests (in terms of timing, edge-triggered vs level-triggered)
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assign nextIntPending = (intPending | (requests & ~intInProgress)) & // requests should raise intPending except when their service routine is already in progress
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~({4{((entry == 24'h200004) & memread)}} << (intClaim-1)); // clear pending bit when claim register is read
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flopr #(N) intPendingFlop(HCLK,~HRESETn,nextIntPending,intPending);
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// pending array - indexed by priority_lvl x source_ID
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genvar i, j;
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for (j=1; j<=7; j++) begin: pending
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for (i=1; i<=N; i=i+1) begin: pendingbit
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assign pendingArray[j][i] = (intPriority[i]==j) & intEn[i] & intPending[i];
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end
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end
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// pending array, except grouped by priority
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assign pendingPGrouped[7:1] = {|pendingArray[7],
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|pendingArray[6],
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|pendingArray[5],
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|pendingArray[4],
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|pendingArray[3],
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|pendingArray[2],
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|pendingArray[1]};
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//assign pendingPGrouped = pendingArray.or;
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// pendingPGrouped, except only topmost priority is active
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assign pendingMaxP[7:1] = {pendingPGrouped[7],
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pendingPGrouped[6] & ~|pendingPGrouped[7],
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pendingPGrouped[5] & ~|pendingPGrouped[7:6],
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pendingPGrouped[4] & ~|pendingPGrouped[7:5],
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pendingPGrouped[3] & ~|pendingPGrouped[7:4],
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pendingPGrouped[2] & ~|pendingPGrouped[7:3],
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pendingPGrouped[1] & ~|pendingPGrouped[7:2]};
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// select the pending requests at that priority
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assign pendingRequestsAtMaxP[N:1] = ({N{pendingMaxP[7]}} & pendingArray[7])
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| ({N{pendingMaxP[6]}} & pendingArray[6])
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| ({N{pendingMaxP[5]}} & pendingArray[5])
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| ({N{pendingMaxP[4]}} & pendingArray[4])
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| ({N{pendingMaxP[3]}} & pendingArray[3])
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| ({N{pendingMaxP[2]}} & pendingArray[2])
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| ({N{pendingMaxP[1]}} & pendingArray[1]);
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// find the lowest ID amongst active interrupts at the highest priority
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logic [5:0] k;
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always_comb begin
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intClaim = 6'b0;
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for (k=N; k>0; k=k-1) begin
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if (pendingRequestsAtMaxP[k]) intClaim = k;
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end
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end
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// create threshold mask
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always_comb begin
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threshMask[7] = (intThreshold != 7);
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threshMask[6] = (intThreshold != 6) & threshMask[7];
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threshMask[5] = (intThreshold != 5) & threshMask[6];
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threshMask[4] = (intThreshold != 4) & threshMask[5];
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threshMask[3] = (intThreshold != 3) & threshMask[4];
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threshMask[2] = (intThreshold != 2) & threshMask[3];
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threshMask[1] = (intThreshold != 1) & threshMask[2];
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end
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// is the max priority > threshold?
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// *** would it be any better to first priority encode maxPriority into binary and then ">" with threshold?
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assign ExtIntM = |(threshMask & pendingPGrouped);
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endmodule
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