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https://github.com/openhwgroup/cvw
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147 lines
11 KiB
Systemverilog
147 lines
11 KiB
Systemverilog
///////////////////////////////////////////
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// ieu.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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//
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// Purpose: Integer Execution Unit: datapath and controller
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//
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// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.12)
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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// https://github.com/openhwgroup/cvw
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module ieu import cvw::*; #(parameter cvw_t P) (
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input logic clk, reset,
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// Decode stage signals
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input logic [31:0] InstrD, // Instruction
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input logic [1:0] STATUS_FS, // is FPU enabled?
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input logic [3:0] ENVCFG_CBE, // Cache block operation enables
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input logic IllegalIEUFPUInstrD, // Illegal instruction
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output logic IllegalBaseInstrD, // Illegal I-type instruction, or illegal RV32 access to upper 16 registers
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// Execute stage signals
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input logic [P.XLEN-1:0] PCE, // PC
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input logic [P.XLEN-1:0] PCLinkE, // PC + 4
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output logic PCSrcE, // Select next PC (between PC+4 and IEUAdrE)
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input logic FWriteIntE, FCvtIntE, // FPU writes to integer register file, FPU converts float to int
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output logic [P.XLEN-1:0] IEUAdrE, // Memory address
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output logic IntDivE, W64E, // Integer divide, RV64 W-type instruction
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output logic [2:0] Funct3E, // Funct3 instruction field
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output logic [P.XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // ALU src inputs before the mux choosing between them and PCE to put in srcA/B
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output logic [4:0] RdE, // Destination register
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output logic MDUActiveE, // Mul/Div instruction being executed
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output logic [3:0] CMOpM, // 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero
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output logic IFUPrefetchE, // instruction prefetch
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output logic LSUPrefetchM, // datata prefetch
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// Memory stage signals
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input logic SquashSCW, // Squash store conditional, from LSU
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output logic [1:0] MemRWE, // Read/write control goes to LSU
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output logic [1:0] MemRWM, // Read/write control goes to LSU
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output logic [1:0] AtomicM, // Atomic control goes to LSU
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output logic [P.XLEN-1:0] WriteDataM, // Write data to LSU
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output logic [2:0] Funct3M, // Funct3 (size and signedness) to LSU
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output logic [P.XLEN-1:0] SrcAM, // ALU SrcA to Privileged unit and FPU
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output logic [4:0] RdM, // Destination register
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input logic [P.XLEN-1:0] FIntResM, // Integer result from FPU (fmv, fclass, fcmp)
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output logic InvalidateICacheM, FlushDCacheM, // Invalidate I$, flush D$
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output logic InstrValidD, InstrValidE, InstrValidM, // Instruction is valid
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output logic BranchD, BranchE,
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output logic JumpD, JumpE,
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// Writeback stage signals
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input logic [P.XLEN-1:0] FIntDivResultW, // Integer divide result from FPU fdivsqrt)
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input logic [P.XLEN-1:0] CSRReadValW, // CSR read value,
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input logic [P.XLEN-1:0] MDUResultW, // multiply/divide unit result
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input logic [P.XLEN-1:0] FCvtIntResW, // FPU's float to int conversion result
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input logic FCvtIntW, // FPU converts float to int
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output logic [4:0] RdW, // Destination register
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input logic [P.XLEN-1:0] ReadDataW, // LSU's read data
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// Hazard unit signals
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input logic StallD, StallE, StallM, StallW, // Stall signals from hazard unit
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input logic FlushD, FlushE, FlushM, FlushW, // Flush signals
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output logic StructuralStallD, // IEU detects structural hazard in Decode stage
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output logic LoadStallD, // Structural stalls for load, sent to performance counters
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output logic StoreStallD, // load after store hazard
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output logic CSRReadM, CSRWriteM, PrivilegedM, // CSR read, CSR write, is privileged instruction
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output logic CSRWriteFenceM, // CSR write or fence instruction needs to flush subsequent instructions
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// Debug scan chain
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input logic DebugScanEn,
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input logic MiscSel,
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input logic GPRSel,
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input logic DebugScanIn,
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input logic GPRScanIn,
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output logic DebugScanOut,
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output logic GPRScanOut,
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input logic DebugCapture,
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input logic DebugRegUpdate,
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input logic [4:0] DebugRegAddr
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);
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logic [2:0] ImmSrcD; // Select type of immediate extension
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logic [1:0] FlagsE; // Comparison flags ({eq, lt})
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logic ALUSrcAE, ALUSrcBE; // ALU source operands
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logic [2:0] ResultSrcW; // Selects result in Writeback stage
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logic ALUResultSrcE; // Selects ALU result to pass on to Memory stage
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logic [2:0] ALUSelectE; // ALU select mux signal
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logic SCE; // Store Conditional instruction
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logic FWriteIntM; // FPU writing to integer register file
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logic IntDivW; // Integer divide instruction
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logic [3:0] BSelectE; // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding
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logic [3:0] ZBBSelectE; // ZBB Result Select Signal in Execute Stage
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logic [2:0] BALUControlE; // ALU Control signals for B instructions in Execute Stage
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logic SubArithE; // Subtraction or arithmetic shift
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logic [6:0] Funct7E;
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// Forwarding signals
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logic [4:0] Rs1D, Rs2D;
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logic [4:0] Rs2E; // Source registers
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logic [1:0] ForwardAE, ForwardBE; // Select signals for forwarding multiplexers
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logic RegWriteM, RegWriteW; // Register will be written in Memory, Writeback stages
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logic MemReadE, CSRReadE; // Load, CSRRead instruction
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logic BranchSignedE; // Branch does signed comparison on operands
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logic MDUE; // Multiply/divide instruction
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logic BMUActiveE; // Bit manipulation instruction being executed
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logic [1:0] CZeroE; // {czero.nez, czero.eqz} instructions active
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logic DSCR; // Debug Scan Chain Register
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controller #(P) c(
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.clk, .reset, .StallD, .FlushD, .InstrD, .STATUS_FS, .ENVCFG_CBE, .ImmSrcD,
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.IllegalIEUFPUInstrD, .IllegalBaseInstrD,
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.StructuralStallD, .LoadStallD, .StoreStallD, .Rs1D, .Rs2D, .Rs2E,
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.StallE, .FlushE, .FlagsE, .FWriteIntE,
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.PCSrcE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .MemReadE, .CSRReadE,
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.Funct3E, .Funct7E, .IntDivE, .MDUE, .W64E, .SubArithE, .BranchD, .BranchE, .JumpD, .JumpE, .SCE,
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.BranchSignedE, .BSelectE, .ZBBSelectE, .BALUControlE, .BMUActiveE, .CZeroE, .MDUActiveE,
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.FCvtIntE, .ForwardAE, .ForwardBE, .CMOpM, .IFUPrefetchE, .LSUPrefetchM,
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.StallM, .FlushM, .MemRWE, .MemRWM, .CSRReadM, .CSRWriteM, .PrivilegedM, .AtomicM, .Funct3M,
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.RegWriteM, .FlushDCacheM, .InstrValidM, .InstrValidE, .InstrValidD, .FWriteIntM,
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.StallW, .FlushW, .RegWriteW, .IntDivW, .ResultSrcW, .CSRWriteFenceM, .InvalidateICacheM,
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.RdW, .RdE, .RdM, .DebugScanEn(DebugScanEn & MiscSel), .DebugScanIn, .DebugScanOut(DSCR));
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datapath #(P) dp(
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.clk, .reset, .ImmSrcD, .InstrD, .Rs1D, .Rs2D, .Rs2E, .StallE, .FlushE, .ForwardAE, .ForwardBE, .W64E, .SubArithE,
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.Funct3E, .Funct7E, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .JumpE, .BranchSignedE,
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.PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE, .BSelectE, .ZBBSelectE, .BALUControlE, .BMUActiveE, .CZeroE,
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.StallM, .FlushM, .FWriteIntM, .FIntResM, .SrcAM, .WriteDataM, .FCvtIntW,
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.StallW, .FlushW, .RegWriteW, .IntDivW, .SquashSCW, .ResultSrcW, .ReadDataW, .FCvtIntResW,
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.CSRReadValW, .MDUResultW, .FIntDivResultW, .RdW, .DebugScanEn, .DebugScanIn(DSCR), .DebugScanOut,
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.MiscSel, .GPRSel, .DebugCapture, .DebugRegUpdate, .DebugRegAddr, .GPRScanIn, .GPRScanOut);
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endmodule
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