mirror of
https://github.com/openhwgroup/cvw
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47 lines
1.7 KiB
C
47 lines
1.7 KiB
C
#pragma once
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#ifndef SPI_HEADER
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#define SPI_HEADER
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#include <stdint.h>
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/* register offsets */
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#define SPI_SCKDIV 0x00 /* Serial clock divisor */
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#define SPI_SCKMODE 0x04 /* Serial clock mode */
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#define SPI_CSID 0x10 /* Chip select ID */
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#define SPI_CSDEF 0x14 /* Chip select default */
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#define SPI_CSMODE 0x18 /* Chip select mode */
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#define SPI_DELAY0 0x28 /* Delay control 0 */
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#define SPI_DELAY1 0x2c /* Delay control 1 */
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#define SPI_FMT 0x40 /* Frame format */
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#define SPI_TXDATA 0x48 /* Tx FIFO data */
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#define SPI_RXDATA 0x4c /* Rx FIFO data */
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#define SPI_TXMARK 0x50 /* Tx FIFO [<35;39;29Mwatermark */
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#define SPI_RXMARK 0x54 /* Rx FIFO watermark */
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/* Non-implemented
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#define SPI_FCTRL 0x60 // SPI flash interface control
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#define SPI_FFMT 0x64 // SPI flash instruction format
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*/
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#define SPI_IE 0x70 /* Interrupt Enable Register */
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#define SPI_IP 0x74 /* Interrupt Pendings Register */
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/* delay0 bits */
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#define SIFIVE_SPI_DELAY0_CSSCK(x) ((u32)(x))
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#define SIFIVE_SPI_DELAY0_CSSCK_MASK 0xffU
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#define SIFIVE_SPI_DELAY0_SCKCS(x) ((u32)(x) << 16)
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#define SIFIVE_SPI_DELAY0_SCKCS_MASK (0xffU << 16)
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/* delay1 bits */
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#define SIFIVE_SPI_DELAY1_INTERCS(x) ((u32)(x))
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#define SIFIVE_SPI_DELAY1_INTERCS_MASK 0xffU
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#define SIFIVE_SPI_DELAY1_INTERXFR(x) ((u32)(x) << 16)
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#define SIFIVE_SPI_DELAY1_INTERXFR_MASK (0xffU << 16)
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void write_reg(uintptr_t addr, uint32_t value);
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uint32_t read_reg(uintptr_t addr);
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uint8_t spi_send_byte(uint8_t byte);
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void spi_init();
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#endif
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