cvw/pipelined/regression
2022-02-27 15:12:10 +00:00
..
slack-notifier Renamed wally-pipelined to pipelined 2022-01-04 19:47:41 +00:00
wave-dos Renamed wallypipelinedhart to wallypipelinedcore 2022-01-20 16:02:08 +00:00
buildrootBugFinder.py update bugfinder script to new file organization 2022-02-15 22:58:18 +00:00
fpga-wave.do More cache cleanup. 2022-02-13 15:47:27 -06:00
lint-wally Added E tests to wally-riscv-arch-test rv32i_m/I and fixed cyclic path in rv32e configuration 2022-02-06 01:22:40 +00:00
linux-wave.do Accidentally cleared dirty bit when setting access bit in hptw. 2022-02-17 16:20:20 -06:00
make-tests.sh Renamed wally-pipelined to pipelined 2022-01-04 19:47:41 +00:00
Makefile Temporarily removed tests/imperas-riscv-tests from Makefile because of license issue 2022-02-27 15:12:10 +00:00
makefile-memfile Completed makefile updates to accelerate the generation of memfiles. There are two makefiles in the 2022-02-03 08:32:48 -06:00
regression-wally Merged TIM and regular testbenches. RV32e now working and back in regression. 2022-02-08 12:18:13 +00:00
sim-buildroot Merged buildroot do files into wally-pipelined do files, added work suffixes so buildroot regression won't fail due to file conflicts 2022-02-05 05:28:40 +00:00
sim-buildroot-batch Modified wally-pipelined-batch.do to handle buildroot 2022-02-05 05:07:07 +00:00
sim-coremark-batch Renamed wally-pipelined to pipelined 2022-01-04 19:47:41 +00:00
sim-fp64 Renamed wally-pipelined to pipelined 2022-01-04 19:47:41 +00:00
sim-fp64-batch Renamed wally-pipelined to pipelined 2022-01-04 19:47:41 +00:00
sim-wally Temporarily changed rv32e config to use TIM, but it still fails. Added rv32e tests. 2022-02-05 04:16:18 +00:00
sim-wally-batch Merged TIM and regular testbenches. RV32e now working and back in regression. 2022-02-08 12:18:13 +00:00
wally-coremark.do Improve wavefile by adding performance counters. 2022-01-12 10:53:29 -06:00
wally-fp64-batch.do Renamed wally-pipelined to pipelined 2022-01-04 19:47:41 +00:00
wally-fp64.do Renamed wally-pipelined to pipelined 2022-01-04 19:47:41 +00:00
wally-harvard.do Added support for logic memory in the IFU and LSU. This disables the bus interface. Peripherals do not work. Also requires using testbench-harvard.sv. I hope to merge this testbench with the main testbench.sv soon. 2022-01-13 22:21:43 -06:00
wally-pipelined-batch.do Added additional suppresses to vsim command incase buildroot files are missing. 2022-02-16 17:05:54 -06:00
wally-pipelined-fpga.do Renamed wally-pipelined to pipelined 2022-01-04 19:47:41 +00:00
wally-pipelined.do Fixed "bug" with wally-pipelined.do 2022-02-22 22:19:25 -06:00
wave-all.do Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault. 2022-01-27 17:11:27 -06:00
wave-coremark.do More cache cleanup. 2022-02-13 15:47:27 -06:00
wave.do change UART PLIC IRQ mapping from 4 to 10 to match virt model; move WALLY-PERIPH tests to wally arch tests 2022-02-22 03:46:08 +00:00