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https://github.com/openhwgroup/cvw
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92 lines
3.4 KiB
Systemverilog
92 lines
3.4 KiB
Systemverilog
/// custom routines defined for the platform
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// Design parameters, used in the code below and custom to this design!
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//`define RAM_PATH soc_top.soc_instance.i_sram_subsystem.i_shared_ram
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//sim:/testbench/dut/uncore/uncore/ram/ram/memory/RAM
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//`define RAM_PATH testbench.dut.uncore.uncore.ram.ram.memory.RAM
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//`define RAM_PATH testbench.dut.uncore.uncore.ram.ram.memory
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`define RAM_PATH testbench.dut.uncoregen.uncore.ram.ram.memory.ram
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//`define RAM_BASE_ADDR 32'h80000000
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`define RAM_BASE_ADDR testbench.P.UNCORE_RAM_BASE
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// These two routines are specific to a particular design. They are used
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// to read and write to the "mailbox" locations, to synchronize behaviors
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// between C code on the processors with activity performed in UVM (and
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// among activities in UVM).
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//
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// Every design will be different. Here we just have a simple Verilog
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// array that we can read and write.
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//
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function automatic void trek_backdoor_read64(
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input longint unsigned address,
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output longint unsigned data,
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input int unsigned debug = 1);
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//bit [15:0] offset = (address-`RAM_BASE_ADDR) >> 2;
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bit [31:0] offset = ((address-`RAM_BASE_ADDR)/(testbench.P.XLEN/8));
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if (address[1:0] != 2'b00) begin: misaligned
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$display("%t trek_backdoor_read64: Misaligned address", $time);
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$finish();
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end
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//data[63:32] = `RAM_PATH[offset + 0];
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//data[31: 0] = `RAM_PATH[offset + 1];
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data[63:0] = `RAM_PATH.RAM[offset + 0];
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if (data != 0)
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$display("%t trek_backdoor_read64: Read 64'h%016h from address 64'h%016h",
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$time, data, address);
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endfunction: trek_backdoor_read64
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function automatic void trek_backdoor_write64(
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input longint unsigned address,
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input longint unsigned data,
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input int unsigned debug = 1);
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//bit [15:0] offset = (address-`RAM_BASE_ADDR) >> 2;
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bit [31:0] offset = ((address-`RAM_BASE_ADDR)/(testbench.P.XLEN/8));
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if (address[1:0] != 2'b00) begin: misaligned
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$display("%t trek_backdoor_write64: Misaligned address", $time);
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$finish();
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end
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//`RAM_PATH[offset + 0] = data[63:32];
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//`RAM_PATH[offset + 1] = data[31: 0];
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`RAM_PATH.RAM[offset + 0] = data[63:0];
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//$display("%t trek_backdoor_write64: Wrote 64'h%016h to address 64'h%016h",
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//$time, data, address);
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endfunction: trek_backdoor_write64
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// For performance, we want to read mailboxes ONLY when they're written to!
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// (This is very important on emulators!)
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//
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// Here we trigger a signal when a memory write happens to the range of
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// addresses where the mailboxes are.
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//
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// A clock later, we go poll all the mailboxes (using the "backdoor_read"
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// method above.
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//
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// Each design will be different, depending on where you are able to snoop
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// for writes and how long it takes a write to propagate from that point
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// to the place where the backdoor read will find it.
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bit trek_c2t_mbox_event;
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bit trek_is_event_addr;
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//assign trek_is_event_addr =
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// ((((`RAM_PATH.ad << 2) + `RAM_BASE_ADDR) >= `TREK_C2T_MBOX_BASE) &&
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// (((`RAM_PATH.ad << 2) + `RAM_BASE_ADDR) < `TREK_C2T_MBOX_LIMIT));
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//
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//always_ff @(posedge `RAM_PATH.clk) begin: trigger_reading_of_mailboxes
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// trek_c2t_mbox_event <= (trek_is_event_addr &&
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// (`RAM_PATH.n_cs == 1'b0) &&
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// (`RAM_PATH.n_we == 1'b0));
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//end
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// Design specifc: one stage delayed so write has a time to settle
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//always @(posedge trek_c2t_mbox_event) begin: read_all_mailboxes
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always @(posedge testbench.clk) begin: read_all_mailboxes
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trek_poll_mbox();
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end
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