Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-01-23 13:04:28 +00:00
Code Issues Packages Projects Releases Wiki Activity
c352353a42
cvw/synthDC
History
David Harris c352353a42 touched extractArea to test commit issue
2023-02-20 11:04:33 -08:00
..
ppa explanations and modifications for general ppa use 2022-07-09 03:24:47 +00:00
scripts Fixed critical range to 50 ps and improved reporting in synthesis 2023-02-20 05:33:33 -08:00
.synopsys_dc.setup Removed redundant compare in setup file 2023-02-19 06:31:26 -08:00
extractArea.pl touched extractArea to test commit issue 2023-02-20 11:04:33 -08:00
extractSummary.py Extraction script updates to match new reports names 2023-02-20 10:16:45 -08:00
Makefile New expression for BTB_SIZE to avoid error during sky90 synthesis 2023-02-20 04:02:00 -08:00
README.md Slight tweaks to synthDC for library variables 2022-02-10 17:56:27 -06:00
wallySynth.py Added noAtomic feature to swweep 2023-02-19 20:05:39 -08:00

README.md

Synthesis for RISC-V Microprocessor System-on-Chip Design

This subdirectory contains synthesis scripts for use with Synopsys (snps) Design Compiler (DC). Synthesis commands are found in scripts/synth.tcl.

Example Usage make synth DESIGN=wallypipelinedcore FREQ=500

environment variables

DESIGN Design provides the name of the output log. Default is synth.

FREQ Frequency in MHz. Default is 500

CONFIG The Wally configuration file. The default is rv32e. Examples: rv32e, rv64gc, rv32gc

TECH The target standard cell library. The default is sky130. sky90: skywater 90nm TT 25C sky130: skywater 130nm TT 25C

SAIFPOWER Controls if power analysis is driven by switching factor or RTL modelsim simulation. When enabled requires a saif file named power.saif. The default is 0. 0: switching factor power analysis 1: RTL simulation driven power analysis.