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slmnemo c15aab9c6f Revert "Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main" 
This reverts commit d601c89d2a, reversing
changes made to 1131d41343.

undid things
2022-05-17 16:54:29 -07:00
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nm_500_MHz_2022-03-22-20-43_2947df5b modified ppa.sv to match module name and added madzscript 2022-05-11 16:13:01 +00:00
scripts Revert "Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main" 2022-05-17 16:54:29 -07:00
.synopsys_dc.setup Cleaned up synthesis warnings 2022-02-11 01:15:16 +00:00
crte_000052064.txt tuning modules for ppa 2022-05-16 15:39:15 +00:00
crte_000055441.txt tuning modules for ppa 2022-05-16 15:39:15 +00:00
extractSummary.py updated makefile to speed up synth 2022-03-07 00:09:18 +00:00
Makefile automate synth 2022-04-25 16:03:32 +00:00
ppa filled in ppa.sv, madzscript.py now synthesizes in parallel in puts results in csv 2022-05-12 07:22:06 +00:00
ppa.py Revert "Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main" 2022-05-17 16:54:29 -07:00
ppaData.csv Revert "Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main" 2022-05-17 16:54:29 -07:00
README.md Slight tweaks to synthDC for library variables 2022-02-10 17:56:27 -06:00
runConfigsSynth.sh Ignore intermediate files in synthesis sweeps 2022-04-27 13:12:04 +00:00
runFrequencySynth.sh Ignore intermediate files in synthesis sweeps 2022-04-27 13:12:04 +00:00
Synopsys_stack_trace_52064.txt tuning modules for ppa 2022-05-16 15:39:15 +00:00
Synopsys_stack_trace_55441.txt tuning modules for ppa 2022-05-16 15:39:15 +00:00

README.md

Synthesis for RISC-V Microprocessor System-on-Chip Design

This subdirectory contains synthesis scripts for use with Synopsys (snps) Design Compiler (DC). Synthesis commands are found in scripts/synth.tcl.

Example Usage make synth DESIGN=wallypipelinedcore FREQ=500

environment variables

DESIGN Design provides the name of the output log. Default is synth.

FREQ Frequency in MHz. Default is 500

CONFIG The Wally configuration file. The default is rv32e. Examples: rv32e, rv64gc, rv32gc

TECH The target standard cell library. The default is sky130. sky90: skywater 90nm TT 25C sky130: skywater 130nm TT 25C

SAIFPOWER Controls if power analysis is driven by switching factor or RTL modelsim simulation. When enabled requires a saif file named power.saif. The default is 0. 0: switching factor power analysis 1: RTL simulation driven power analysis.