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https://github.com/openhwgroup/cvw
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117 lines
4.0 KiB
C
117 lines
4.0 KiB
C
///////////////////////////////////////////////////////////////////////
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// spi.h
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//
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// Written: Jaocb Pease jacob.pease@okstate.edu 7/22/2024
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//
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// Purpose: Header file for interfaceing with the SPI peripheral
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//
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//
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the
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// “License”); you may not use this file except in compliance with the
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// License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work
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// distributed under the License is distributed on an “AS IS” BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
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// implied. See the License for the specific language governing
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// permissions and limitations under the License.
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///////////////////////////////////////////////////////////////////////
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#pragma once
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#ifndef SPI_HEADER
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#define SPI_HEADER
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#include <stdint.h>
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#define SPI_BASE 0x13000 /* Base address of SPI device used for SDC */
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/* register offsets */
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#define SPI_SCKDIV SPI_BASE + 0x00 /* Serial clock divisor */
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#define SPI_SCKMODE SPI_BASE + 0x04 /* Serial clock mode */
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#define SPI_CSID SPI_BASE + 0x10 /* Chip select ID */
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#define SPI_CSDEF SPI_BASE + 0x14 /* Chip select default */
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#define SPI_CSMODE SPI_BASE + 0x18 /* Chip select mode */
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#define SPI_DELAY0 SPI_BASE + 0x28 /* Delay control 0 */
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#define SPI_DELAY1 SPI_BASE + 0x2c /* Delay control 1 */
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#define SPI_FMT SPI_BASE + 0x40 /* Frame format */
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#define SPI_TXDATA SPI_BASE + 0x48 /* Tx FIFO data */
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#define SPI_RXDATA SPI_BASE + 0x4c /* Rx FIFO data */
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#define SPI_TXMARK SPI_BASE + 0x50 /* Tx FIFO [<35;39;29Mwatermark */
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#define SPI_RXMARK SPI_BASE + 0x54 /* Rx FIFO watermark */
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/* Non-implemented
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#define SPI_FCTRL SPI_BASE + 0x60 // SPI flash interface control
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#define SPI_FFMT SPI_BASE + 0x64 // SPI flash instruction format
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*/
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#define SPI_IE SPI_BASE + 0x70 /* Interrupt Enable Register */
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#define SPI_IP SPI_BASE + 0x74 /* Interrupt Pendings Register */
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/* delay0 bits */
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#define SIFIVE_SPI_DELAY0_CSSCK(x) ((uint32_t)(x))
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#define SIFIVE_SPI_DELAY0_CSSCK_MASK 0xffU
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#define SIFIVE_SPI_DELAY0_SCKCS(x) ((uint32_t)(x) << 16)
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#define SIFIVE_SPI_DELAY0_SCKCS_MASK (0xffU << 16)
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/* delay1 bits */
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#define SIFIVE_SPI_DELAY1_INTERCS(x) ((uint32_t)(x))
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#define SIFIVE_SPI_DELAY1_INTERCS_MASK 0xffU
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#define SIFIVE_SPI_DELAY1_INTERXFR(x) ((uint32_t)(x) << 16)
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#define SIFIVE_SPI_DELAY1_INTERXFR_MASK (0xffU << 16)
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/* csmode bits */
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#define SIFIVE_SPI_CSMODE_MODE_AUTO 0U
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#define SIFIVE_SPI_CSMODE_MODE_HOLD 2U
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#define SIFIVE_SPI_CSMODE_MODE_OFF 3U
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// inline void write_reg(uintptr_t addr, uint32_t value);
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//inline uint32_t read_reg(uintptr_t addr);
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//inline void spi_sendbyte(uint8_t byte);
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//inline void waittx();
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//inline void waitrx();
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uint8_t spi_txrx(uint8_t byte);
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uint8_t spi_dummy();
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//inline uint8_t spi_readbyte();
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uint64_t spi_read64();
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void spi_init();
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void spi_set_clock(uint32_t clkin, uint32_t clkout);
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static inline void write_reg(uintptr_t addr, uint32_t value) {
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volatile uint32_t * loc = (volatile uint32_t *) addr;
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*loc = value;
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}
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// Read a register
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static inline uint32_t read_reg(uintptr_t addr) {
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return *(volatile uint32_t *) addr;
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}
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// Queues a single byte in the transfer fifo
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static inline void spi_sendbyte(uint8_t byte) {
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// Write byte to transfer fifo
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write_reg(SPI_TXDATA, byte);
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}
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static inline void waittx() {
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while(!(read_reg(SPI_IP) & 1)) {}
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}
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static inline void waitrx() {
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while(read_reg(SPI_IP) & 2) {}
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}
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static inline uint8_t spi_readbyte() {
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return read_reg(SPI_RXDATA);
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}
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#endif
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