mirror of
https://github.com/openhwgroup/cvw
synced 2025-01-23 13:04:28 +00:00
53 lines
1.9 KiB
Tcsh
53 lines
1.9 KiB
Tcsh
#!/bin/csh
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# site-setup.csh
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# License servers and commercial CAD tool paths
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# Must edit these based on your local environment. Ask your sysadmin.
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setenv MGLS_LICENSE_FILE 27002@zircon.eng.hmc.edu # Change this to your Siemens license server
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setenv SNPSLMD_LICENSE_FILE 27020@zircon.eng.hmc.edu # Change this to your Synopsys license server
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setenv QUESTAPATH /cad/mentor/questa_sim-2022.4_2/questasim/bin # Change this for your path to Questa
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setenv SNPSPATH /cad/synopsys/SYN/bin # Change this for your path to Design Compiler
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setenv VCSPATH /cad/synopsys/vcs/U-2023.03-SP2-4/bin # Change this for your path to Synopsys VCS
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# Tools
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# Questa and Synopsys
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extend PATH $QUESTAPATH
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extend PATH $SNPSPATH
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extend PATH $VCSPATH
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# GCC
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extend LD_LIBRARY_PATH $RISCV/riscv64-unknown-elf/lib
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# RISC-V Tools
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extend LD_LIBRARY_PATH $RISCV/lib
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extend LD_LIBRARY_PATH $RISCV/lib64
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extend PATH $RISCV/bin
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# Activate riscv-python Virtual Environment
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source "$RISCV"/riscv-python/bin/activate
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# environment variables needed for RISCV-DV
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setenv RISCV_GCC $(which riscv64-unknown-elf-gcc) # Copy this as it is
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setenv RISCV_OBJCOPY $(which riscv64-unknown-elf-objcopy) # Copy this as it is
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setenv SPIKE_PATH $RISCV/bin # Change this for your path to riscv-isa-sim (spike)
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# Verilator needs a larger stack to simulate CORE-V Wally
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limit stacksize unlimited
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# Imperas; put this in if you are using it
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#set path = ($RISCV/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64 $path)
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#setenv LD_LIBRARY_PATH $RISCV/imperas_riscv_tests/riscv-ovpsim-plus/bin/Linux64:$LD_LIBRARY_PATH # remove if no imperas
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setenv IDV $RISCV/ImperasDV-OpenHW
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if ($?IDV) then
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# echo "Imperas exists"
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setenv IMPERAS_HOME $IDV/Imperas
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setenv IMPERAS_PERSONALITY CPUMAN_DV_ASYNC
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setenv ROOTDIR ~/
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source ${IMPERAS_HOME}/bin/setup.sh
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setupImperas ${IMPERAS_HOME}
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extend PATH $IDV/scripts/cvw
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endfi
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