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https://github.com/openhwgroup/cvw
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185 lines
8.7 KiB
Systemverilog
185 lines
8.7 KiB
Systemverilog
///////////////////////////////////////////
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// csrm.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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//
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// Purpose: Machine-Mode Control and Status Registers
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// See RISC-V Privileged Mode Specification 20190608
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module csrm #(parameter
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// Machine CSRs
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MVENDORID = 12'hF11,
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MARCHID = 12'hF12,
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MIMPID = 12'hF13,
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MHARTID = 12'hF14,
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MSTATUS = 12'h300,
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MISA_ADR = 12'h301,
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MEDELEG = 12'h302,
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MIDELEG = 12'h303,
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MIE = 12'h304,
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MTVEC = 12'h305,
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MCOUNTEREN = 12'h306,
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MSTATUSH = 12'h310,
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MCOUNTINHIBIT = 12'h320,
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MSCRATCH = 12'h340,
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MEPC = 12'h341,
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MCAUSE = 12'h342,
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MTVAL = 12'h343,
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MIP = 12'h344,
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PMPCFG0 = 12'h3A0,
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PMPCFG1 = 12'h3A1,
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PMPCFG2 = 12'h3A2,
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PMPCFG3 = 12'h3A3,
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PMPADDR0 = 12'h3B0,
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//... more physical memory protection
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PMPADDR15 = 12'h3BF,
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TSELECT = 12'h7A0,
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TDATA1 = 12'h7A1,
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TDATA2 = 12'h7A2,
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TDATA3 = 12'h7A3,
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DCSR = 12'h7B0,
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DPC = 12'h7B1,
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DSCRATCH0 = 12'h7B2,
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DSCRATCH1 = 12'h7B3) (
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input logic clk, reset,
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input logic CSRMWriteM, MTrapM,
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input logic [11:0] CSRAdrM,
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input logic [`XLEN-1:0] NextEPCM, NextCauseM, NextMtvalM, MSTATUS_REGW,
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input logic [`XLEN-1:0] CSRWriteValM,
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output logic [`XLEN-1:0] CSRMReadValM, MEPC_REGW, MTVEC_REGW,
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output logic [31:0] MCOUNTEREN_REGW, MCOUNTINHIBIT_REGW,
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output logic [`XLEN-1:0] MEDELEG_REGW, MIDELEG_REGW,
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input logic [11:0] MIP_REGW, MIE_REGW,
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output logic WriteMSTATUSM,
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output logic IllegalCSRMAccessM
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);
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logic [`XLEN-1:0] MISA_REGW;
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logic [`XLEN-1:0] MSCRATCH_REGW,MCAUSE_REGW, MTVAL_REGW;
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logic [63:0] PMPCFG01_REGW, PMPCFG23_REGW; // 64-bit registers in RV64, or two 32-bit registers in RV32
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logic [`XLEN-1:0] PMPADDR0_REGW; // will need to add more
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logic [`XLEN-1:0] zero = 0;
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logic [31:0] allones = {32{1'b1}};
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logic [`XLEN-1:0] MEDELEG_MASK = ~(zero | 1'b1 << 11); // medeleg[11] hardwired to zero per Privileged Spec 3.1.8
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logic [`XLEN-1:0] MIDELEG_MASK = {{(`XLEN-12){1'b0}}, 12'h222}; // only allow delegating interrupts to supervisor mode
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logic WriteMTVECM, WriteMEDELEGM, WriteMIDELEGM;
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logic WriteMSCRATCHM, WriteMEPCM, WriteMCAUSEM, WriteMTVALM;
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logic WriteMCOUNTERENM, WriteMCOUNTINHIBITM;
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logic WritePMPCFG0M, WritePMPCFG2M;
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logic WritePMPADDR0M;
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logic [25:0] MISAbits = `MISA;
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// MISA is hardwired. Spec says it could be written to disable features, but this is not supported by Wally
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assign MISA_REGW = {(`XLEN == 32 ? 2'b01 : 2'b10), {(`XLEN-28){1'b0}}, MISAbits};
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// Write machine Mode CSRs
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assign WriteMSTATUSM = CSRMWriteM && (CSRAdrM == MSTATUS);
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assign WriteMTVECM = CSRMWriteM && (CSRAdrM == MTVEC);
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assign WriteMEDELEGM = CSRMWriteM && (CSRAdrM == MEDELEG);
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assign WriteMIDELEGM = CSRMWriteM && (CSRAdrM == MIDELEG);
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assign WriteMSCRATCHM = CSRMWriteM && (CSRAdrM == MSCRATCH);
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assign WriteMEPCM = MTrapM | (CSRMWriteM && (CSRAdrM == MEPC));
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assign WriteMCAUSEM = MTrapM | (CSRMWriteM && (CSRAdrM == MCAUSE));
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assign WriteMTVALM = MTrapM | (CSRMWriteM && (CSRAdrM == MTVAL));
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assign WritePMPCFG0M = (CSRMWriteM && (CSRAdrM == PMPCFG0));
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assign WritePMPCFG2M = (CSRMWriteM && (CSRAdrM == PMPCFG2));
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assign WritePMPADDR0M = (CSRMWriteM && (CSRAdrM == PMPADDR0));
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assign WriteMCOUNTERENM = CSRMWriteM && (CSRAdrM == MCOUNTEREN);
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assign WriteMCOUNTINHIBITM = CSRMWriteM && (CSRAdrM == MCOUNTINHIBIT);
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// CSRs
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flopenl #(`XLEN) MTVECreg(clk, reset, WriteMTVECM, CSRWriteValM, `XLEN'b0, MTVEC_REGW); //busybear: changed reset value to 0
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generate
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if (`S_SUPPORTED | (`U_SUPPORTED & `N_SUPPORTED)) begin // DELEG registers should exist
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flopenl #(`XLEN) MEDELEGreg(clk, reset, WriteMEDELEGM, CSRWriteValM & MEDELEG_MASK, zero, MEDELEG_REGW);
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flopenl #(`XLEN) MIDELEGreg(clk, reset, WriteMIDELEGM, CSRWriteValM & MIDELEG_MASK, zero, MIDELEG_REGW);
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end else begin
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assign MEDELEG_REGW = 0;
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assign MIDELEG_REGW = 0;
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end
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endgenerate
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// flopenl #(`XLEN) MIPreg(clk, reset, WriteMIPM, CSRWriteValM, zero, MIP_REGW);
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// flopenl #(`XLEN) MIEreg(clk, reset, WriteMIEM, CSRWriteValM, zero, MIE_REGW);
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flopenr #(`XLEN) MSCRATCHreg(clk, reset, WriteMSCRATCHM, CSRWriteValM, MSCRATCH_REGW);
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flopenr #(`XLEN) MEPCreg(clk, reset, WriteMEPCM, NextEPCM, MEPC_REGW);
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flopenr #(`XLEN) MCAUSEreg(clk, reset, WriteMCAUSEM, NextCauseM, MCAUSE_REGW);
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flopenr #(`XLEN) MTVALreg(clk, reset, WriteMTVALM, NextMtvalM, MTVAL_REGW);
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`ifndef BUSYBEAR
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flopenl #(32) MCOUNTERENreg(clk, reset, WriteMCOUNTERENM, CSRWriteValM[31:0], allones, MCOUNTEREN_REGW);
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`else
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flopenl #(32) MCOUNTERENreg(clk, reset, WriteMCOUNTERENM, {CSRWriteValM[31:2],1'b0,CSRWriteValM[0]}, 32'b0, MCOUNTEREN_REGW);
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`endif
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flopenl #(32) MCOUNTINHIBITreg(clk, reset, WriteMCOUNTINHIBITM, CSRWriteValM[31:0], allones, MCOUNTINHIBIT_REGW);
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flopenr #(`XLEN) PMPADDR0reg(clk, reset, WritePMPADDR0M, CSRWriteValM, PMPADDR0_REGW);
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// PMPCFG registers are a pair of 64-bit in RV64 and four 32-bit in RV32
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generate
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if (`XLEN==64) begin
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flopenr #(`XLEN) PMPCFG01reg(clk, reset, WritePMPCFG0M, CSRWriteValM, PMPCFG01_REGW);
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flopenr #(`XLEN) PMPCFG23reg(clk, reset, WritePMPCFG2M, CSRWriteValM, PMPCFG23_REGW);
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end else begin
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logic WritePMPCFG1M, WritePMPCFG3M;
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assign WritePMPCFG1M = MTrapM | (CSRMWriteM && (CSRAdrM == PMPCFG1));
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assign WritePMPCFG3M = MTrapM | (CSRMWriteM && (CSRAdrM == PMPCFG3));
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flopenr #(`XLEN) PMPCFG0reg(clk, reset, WritePMPCFG0M, CSRWriteValM, PMPCFG01_REGW[31:0]);
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flopenr #(`XLEN) PMPCFG1reg(clk, reset, WritePMPCFG1M, CSRWriteValM, PMPCFG01_REGW[63:32]);
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flopenr #(`XLEN) PMPCFG2reg(clk, reset, WritePMPCFG2M, CSRWriteValM, PMPCFG23_REGW[31:0]);
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flopenr #(`XLEN) PMPCFG3reg(clk, reset, WritePMPCFG3M, CSRWriteValM, PMPCFG23_REGW[63:32]);
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end
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endgenerate
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// Read machine mode CSRs
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always_comb begin
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IllegalCSRMAccessM = !(`S_SUPPORTED | `U_SUPPORTED & `N_SUPPORTED) &&
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(CSRAdrM == MEDELEG || CSRAdrM == MIDELEG); // trap on DELEG register access when no S or N-mode
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case (CSRAdrM)
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MISA_ADR: CSRMReadValM = MISA_REGW;
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MVENDORID: CSRMReadValM = 0;
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MARCHID: CSRMReadValM = 0;
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MIMPID: CSRMReadValM = 'h100; // pipelined implementation
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MHARTID: CSRMReadValM = 0;
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MSTATUS: CSRMReadValM = MSTATUS_REGW;
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MSTATUSH: CSRMReadValM = 0; // flush this out later if MBE and SBE fields are supported
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MTVEC: CSRMReadValM = MTVEC_REGW;
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MEDELEG: CSRMReadValM = MEDELEG_REGW;
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MIDELEG: CSRMReadValM = MIDELEG_REGW;
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MIP: CSRMReadValM = {{(`XLEN-12){1'b0}}, MIP_REGW};
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MIE: CSRMReadValM = {{(`XLEN-12){1'b0}}, MIE_REGW};
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MSCRATCH: CSRMReadValM = MSCRATCH_REGW;
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MEPC: CSRMReadValM = MEPC_REGW;
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MCAUSE: CSRMReadValM = MCAUSE_REGW;
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MTVAL: CSRMReadValM = MTVAL_REGW;
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MCOUNTEREN:CSRMReadValM = {{(`XLEN-32){1'b0}}, MCOUNTEREN_REGW};
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MCOUNTINHIBIT:CSRMReadValM = {{(`XLEN-32){1'b0}}, MCOUNTINHIBIT_REGW};
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PMPCFG0: CSRMReadValM = PMPCFG01_REGW[`XLEN-1:0];
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PMPCFG1: CSRMReadValM = {{(`XLEN-32){1'b0}}, PMPCFG01_REGW[63:31]};
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PMPCFG2: CSRMReadValM = PMPCFG23_REGW[`XLEN-1:0];
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PMPCFG3: CSRMReadValM = {{(`XLEN-32){1'b0}}, PMPCFG23_REGW[63:31]};
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PMPADDR0: CSRMReadValM = PMPADDR0_REGW;
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default: begin
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CSRMReadValM = 0;
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IllegalCSRMAccessM = 1;
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end
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endcase
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end
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endmodule
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