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90 lines
3.9 KiB
Systemverilog
90 lines
3.9 KiB
Systemverilog
///////////////////////////////////////////
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// csri.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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//
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// Purpose: Interrupt Control & Status Registers (IP, EI)
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// See RISC-V Privileged Mode Specification 20190608 & 20210108 draft
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//
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// Documentation: RISC-V System on Chip Design Chapter 5
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module csri #(parameter
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MIE = 12'h304,
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MIP = 12'h344,
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SIE = 12'h104,
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SIP = 12'h144) (
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input logic clk, reset,
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input logic InstrValidNotFlushedM,
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input logic CSRMWriteM, CSRSWriteM,
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input logic [`XLEN-1:0] CSRWriteValM,
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input logic [11:0] CSRAdrM,
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input logic MExtInt, SExtInt, MTimerInt, STimerInt, MSwInt,
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output logic [11:0] MIP_REGW, MIE_REGW,
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output logic [11:0] MIP_REGW_writeable // only SEIP, STIP, SSIP are actually writeable; the rest are hardwired to 0
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);
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logic [11:0] MIP_WRITE_MASK, SIP_WRITE_MASK, MIE_WRITE_MASK;
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logic WriteMIPM, WriteMIEM, WriteSIPM, WriteSIEM;
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logic STIP;
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// Interrupt Write Enables
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assign WriteMIPM = CSRMWriteM & (CSRAdrM == MIP) & InstrValidNotFlushedM;
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assign WriteMIEM = CSRMWriteM & (CSRAdrM == MIE) & InstrValidNotFlushedM;
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assign WriteSIPM = CSRSWriteM & (CSRAdrM == SIP) & InstrValidNotFlushedM;
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assign WriteSIEM = CSRSWriteM & (CSRAdrM == SIE) & InstrValidNotFlushedM;
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// Interrupt Pending and Enable Registers
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// MEIP, MTIP, MSIP are read-only
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// SEIP, STIP, SSIP is writable in MIP if S mode exists
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// SSIP is writable in SIP if S mode exists
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if (`S_SUPPORTED) begin:mask
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if (`SSTC_SUPPORTED) begin
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assign MIP_WRITE_MASK = 12'h202; // SEIP and SSIP are writable, but STIP is not writable when STIMECMP is implemented (see SSTC spec)
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assign STIP = STimerInt;
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end else begin
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assign MIP_WRITE_MASK = 12'h222; // SEIP, STIP, SSIP are writeable in MIP (20210108-draft 3.1.9)
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assign STIP = MIP_REGW_writeable[5];
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end
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assign SIP_WRITE_MASK = 12'h002; // SSIP is writeable in SIP (privileged 20210108-draft 4.1.3)
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assign MIE_WRITE_MASK = 12'hAAA;
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end else begin:mask
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assign MIP_WRITE_MASK = 12'h000;
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assign SIP_WRITE_MASK = 12'h000;
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assign MIE_WRITE_MASK = 12'h888;
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end
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always @(posedge clk)
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if (reset) MIP_REGW_writeable <= 12'b0;
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else if (WriteMIPM) MIP_REGW_writeable <= (CSRWriteValM[11:0] & MIP_WRITE_MASK);
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else if (WriteSIPM) MIP_REGW_writeable <= (CSRWriteValM[11:0] & SIP_WRITE_MASK) | (MIP_REGW_writeable & ~SIP_WRITE_MASK);
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always @(posedge clk)
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if (reset) MIE_REGW <= 12'b0;
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else if (WriteMIEM) MIE_REGW <= (CSRWriteValM[11:0] & MIE_WRITE_MASK); // MIE controls M and S fields
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else if (WriteSIEM) MIE_REGW <= (CSRWriteValM[11:0] & 12'h222) | (MIE_REGW & 12'h888); // only S fields
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assign MIP_REGW = {MExtInt, 1'b0, SExtInt|MIP_REGW_writeable[9], 1'b0,
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MTimerInt, 1'b0, STIP, 1'b0,
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MSwInt, 1'b0, MIP_REGW_writeable[1], 1'b0};
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endmodule
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