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60 lines
2.3 KiB
Systemverilog
60 lines
2.3 KiB
Systemverilog
///////////////////////////////////////////
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// simpleram.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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//
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// Purpose: On-chip SIMPLERAM, external to core
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module simpleram #(parameter BASE=0, RANGE = 65535) (
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input logic clk,
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input logic [31:0] a,
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input logic we,
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input logic [`XLEN/8-1:0] ByteMask,
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input logic [`XLEN-1:0] wd,
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output logic [`XLEN-1:0] rd
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);
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logic [`XLEN-1:0] RAM[BASE>>(1+`XLEN/32):(RANGE+BASE)>>1+(`XLEN/32)];
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// discard bottom 2 or 3 bits of address offset within word or doubleword
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localparam adrlsb = (`XLEN==64) ? 3 : 2;
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logic [31:adrlsb] adrmsbs;
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assign adrmsbs = a[31:adrlsb];
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always_ff @(posedge clk)
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rd <= RAM[adrmsbs];
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genvar index;
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for(index = 0; index < `XLEN/8; index++) begin
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always_ff @(posedge clk) begin
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if (we & ByteMask[index]) RAM[adrmsbs][8*(index+1)-1:8*index] <= #1 wd[8*(index+1)-1:8*index];
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end
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end
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endmodule
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