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			153 lines
		
	
	
		
			3.8 KiB
		
	
	
	
		
			ArmAsm
		
	
	
	
	
	
			
		
		
	
	
			153 lines
		
	
	
		
			3.8 KiB
		
	
	
	
		
			ArmAsm
		
	
	
	
	
	
///////////////////////////////////////////
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// tlbMisaligned.S
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//
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// Written: Rose Thompson rose@rosethompson.net
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//
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// Purpose: Create a page table with misaligned load and store access.  Checks TLB misses prevent misaligned load/store fault.
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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// https://github.com/openhwgroup/cvw
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//
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// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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// load code to initalize stack, handle interrupts, terminate
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#include "WALLY-init-lib.h"
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# run-elf.bash find this in project description
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main:
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    li t5, 0x1
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    slli t5, t5, 62
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    ori t5, t5, 0xF0
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    csrs menvcfg, t5  # menvcfg.PBMTE = 1, CBZE, CBCFE, CBIE all 1
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    # Page table root address at 0x80010000
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    li t5, 0x9000000000080010
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    csrw satp, t5
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    # sfence.vma x0, x0
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    # switch to supervisor mode
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    li a0, 1
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    ecall
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    li t5, 0
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    li t2, 0x1000
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    li t0, 0x1000 // go to first gigapage
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    li t4, 0x40000000 // put this outside the loop.
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    lw t1, 1(t0) # load a misaligned aligned cached address
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    li t1, 0x00008067 #load in jalr
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    add t0, t0, t2 # go to the next page
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    sw t1, 1(t0) # store to another misaligned cached address.
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    add t0, t0, t2 # go to the next page
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    lw t1, 1(t0) # load a misaligned aligned uncached address should fault
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    add t0, t0, t2 # go to the next page
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    sw t1, 1(t0) # store to another misaligned uncached address should falt.
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    fence.I
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finished:
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    j done
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.data
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.align 16
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# Page table situated at 0x80010000
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pagetable:
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    .8byte 0x200044C1
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.align 12
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    .8byte 0x00000000200048C1
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    .8byte 0x00000000200048C1
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    .8byte 0x00000000200048C1
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.align 12
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    .8byte 0x0000000020004CC1
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    //.8byte 0x00000200800CF// ADD IN THE MEGAPAGE should 3 nibbles of zeros be removed?
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.align 12
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    #80000000
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    .8byte 0x200000CF
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    .8byte 0x200004CF  # first page
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    .8byte 0x200008CF  # second page
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    .8byte 0x2000000020000CCF  # 3rd page
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    .8byte 0x20000000200010CF  # 4th page
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    .8byte 0x200014CF
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    .8byte 0x200018CF
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    .8byte 0x20001CCF
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    .8byte 0x200020CF
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    .8byte 0x200024CF
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    .8byte 0x200028CF
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    .8byte 0x20002CCF
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    .8byte 0x200030CF
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    .8byte 0x200034CF
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    .8byte 0x200038CF
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    .8byte 0x20003CCF
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    .8byte 0x200040CF
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    .8byte 0x200044CF
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    .8byte 0x200048CF
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    .8byte 0x20004CCF
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    .8byte 0x200050CF
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    .8byte 0x200054CF
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    .8byte 0x200058CF
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    .8byte 0x20005CCF
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    .8byte 0x200060CF
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    .8byte 0x200064CF
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    .8byte 0x200068CF
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    .8byte 0x20006CCF
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    .8byte 0x200070CF
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    .8byte 0x200074CF
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    .8byte 0x200078CF
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    .8byte 0x20007CCF
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    .8byte 0x200080CF
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    .8byte 0x200084CF
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    .8byte 0x200088CF
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    .8byte 0x20008CCF
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    .8byte 0x200090CF
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    .8byte 0x200094CF
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    .8byte 0x200098CF
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    .8byte 0x20009CCF
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    .8byte 0x2000A0CF
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    .8byte 0x2000A4CF
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    .8byte 0x2000A8CF
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    .8byte 0x2000ACCF
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    .8byte 0x2000B0CF
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    .8byte 0x2000B4CF
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    .8byte 0x2000B8CF
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    .8byte 0x2000BCCF
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    .8byte 0x2000C0CF
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    .8byte 0x2000C4CF
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    .8byte 0x2000C8CF
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    .8byte 0x2000CCCF
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    .8byte 0x2000D0CF
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    .8byte 0x2000D4CF
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