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Configurable RISC-V Processor
381 Commits 5 Branches 2 Tags 53 MiB
SystemVerilog 33.7%
Python 19.2%
Assembly 17.5%
Tcl 16.2%
C 5.8%
Other 7.4%
bc1a0c6ee7
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Noah Boorstin bc1a0c6ee7 change ifndef to generate/if
2021-03-18 12:50:19 -04:00
sky130 sky130 18T and 15T cell libraries removed 2021-02-14 09:05:41 -06:00
wally-pipelined change ifndef to generate/if 2021-03-18 12:50:19 -04:00
.gitignore Added debug option to disable the function radix if not needed. 2021-03-10 15:17:02 -06:00
.gitmodules sky130 18T and 15T cell libraries removed 2021-02-14 09:05:41 -06:00
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README.md

README.md

riscv-wally

Configurable RISC-V Processor