Ross Thompson a11597b6bd Added more debugging code for FPGA.		2021-12-17 14:40:25 -06:00
..
csr.sv	manually resolved git merge conflicts in testbench linux after checkpointing	2021-10-24 15:02:19 -07:00
csrc.sv	Added more debugging code for FPGA.	2021-12-17 14:40:25 -06:00
csri.sv	Synchronous reset in non-flop blocks	2021-10-26 08:30:35 -07:00
csrm.sv	Merge branch 'main' into fpga	2021-10-20 16:24:55 -05:00
csrn.sv	Gave names to for loops in generate blocks for ease of reference	2021-07-04 18:52:16 -04:00
csrs.sv	Merge branch 'main' into fpga	2021-11-29 10:06:53 -06:00
csrsr.sv	merging changes	2021-10-26 08:34:36 -07:00
csru.sv	Cleaned up LINT erors	2021-10-23 06:28:49 -07:00
privdec.sv	Implemented TSR, TW, TVM, MXR status bits	2021-07-06 01:32:05 -04:00
privileged.sv	Added more debugging code for FPGA.	2021-12-17 14:40:25 -06:00
trap.sv	Merge branch 'main' into fpga	2021-11-29 10:06:53 -06:00