mirror of
https://github.com/openhwgroup/cvw
synced 2025-01-23 04:54:29 +00:00
170 lines
3.4 KiB
Plaintext
170 lines
3.4 KiB
Plaintext
# General file extensions to ignore
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.nfs*
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*.objdump*
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*.o
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*.d
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*.a
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*.vstf
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*.vcd
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*.signature.output
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*.dtb
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*.log
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*.map
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*.elf*
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*.list
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# General directories to ignore
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.vscode/
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__pycache__/
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**/work*
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!.github/workflows/*
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/**/obj_dir*
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/**/gmon*
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# Tests
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tests/riscof/config32.ini
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tests/riscof/config32e.ini
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tests/riscof/config64.ini
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tests/riscof/riscof_work/
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tests/wally-riscv-arch-test/riscv-test-suite/*/I/*/**
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tests/fp/vectors/*.tv
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tests/fp/vectors/sed*
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tests/fp/combined_IF_vectors/IF_vectors/*.tv
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tests/custom/*/*/
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tests/custom/*/*/*.memfile
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sim/tests/riscvdv
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# Linux
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linux/buildroot
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linux/testvector-generation/boottrace.S
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linux/devicetree/debug/*
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!linux/devicetree/debug/dump-dts.sh
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linux/testvector-generation/genCheckpoint.gdb
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linux/testvector-generation/silencePipe
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linux/testvector-generation/silencePipe.control
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linux/testvector-generation/fixBinMem
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linux/testvector-generation/qemu-serial
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# FPGA
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fpga/generator/IP
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fpga/generator/vivado.*
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fpga/generator/.Xil/*
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fpga/generator/WallyFPGA*
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fpga/generator/reports/
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fpga/generator/*.jou
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fpga/src/sdc/*
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fpga/src/sdc.tar.gz
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fpga/src/CopiedFiles_do_not_add_to_repo/*
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fpga/generator/sim/imp-funcsim.v
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fpga/generator/sim/imp-timesim.sdf
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fpga/generator/sim/imp-timesim.v
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fpga/generator/sim/syn-funcsim.v
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fpga/rvvidaemon/rvvidaemon
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fpga/zsbl/OBJ/*
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fpga/zsbl/bin/*
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fpga/src/boot.mem
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fpga/src/data.mem
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# Synthesis
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synthDC/WORK
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synthDC/alib-52
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synthDC/*.svf
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synthDC/runs/
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synthDC/newRuns
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synthDC/ppa/PPAruns
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synthDC/ppa/plots
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synthDC/wallyplots/
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synthDC/runArchive
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synthDC/hdl
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synthDC/Summary.csv
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# Benchmarks
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benchmarks/embench/wally*.json
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benchmarks/embench/run*
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benchmarks/coremark/coremark_results.csv
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# Simulation
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sim/*.svg
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sim/power.saif
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sim/results
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sim/results-error/
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sim/test1.rep
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sim/branch
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sim/branch-march14.tar.gz
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sim/gshareforward-no-class
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sim/local16.txt
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sim/localhistory_m6k10_results_april24.txt
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sim/cfi/*
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sim/branch/*
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sim/covhtmlreport/
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sim/*/*Cache.log
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# Questa
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sim/questa/logs
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sim/questa/wkdir
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sim/questa/ucdb
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sim/questa/cov
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sim/questa/fcov
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sim/questa/fcovrvvi
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sim/questa/fcovrvvi_logs
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sim/questa/fcovrvvi_ucdb
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sim/questa/fcov_logs
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sim/questa/fcov_ucdb
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sim/questa/riscv.ucdb
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transcript
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vsim.wlf
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wlft*
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# VCS
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sim/vcs/logs
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sim/vcs/wkdir
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sim/vcs/ucdb
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sim/vcs/csrc
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sim/vcs/profileReport*
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sim/vcs/program.out
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sim/vcs/sim_out*
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sim/vcs/simprofile_dir
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sim/vcs/ucli.key
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sim/vcs/verdi_config_file
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sim/vcs/vcdplus.vpd
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sim/vcs/simprofile*
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# Verilator
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sim/verilator/logs
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sim/verilator/wkdir
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# Examples
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examples/verilog/fulladder/csrc/
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examples/verilog/fulladder/profileReport.html
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examples/verilog/fulladder/profileReport.json
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examples/verilog/fulladder/profileReport.txt
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examples/verilog/fulladder/profileReport/
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examples/verilog/fulladder/simprofile_dir/
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examples/verilog/fulladder/simv.daidir/
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examples/verilog/fulladder/ucli.key
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examples/verilog/fulladder/verdi_config_file
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examples/fp/softfloat_demo/softfloat_demo
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examples/fp/softfloat_demo/softfloat_demoDP
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examples/fp/softfloat_demo/softfloat_demoQP
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examples/fp/softfloat_demo/softfloat_demoSP
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examples/fp/fpcalc/fpcalc
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examples/fp/sqrttest/sqrttest
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examples/crypto/gfmul/gfmul
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examples/C/fir/fir
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examples/C/inline/inline
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examples/C/mcmodel/mcmodel_medany
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examples/C/mcmodel/mcmodel_medlow
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examples/C/sum/sum
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examples/C/sum_mixed/sum_mixed
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examples/asm/sumtest/sumtest
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examples/asm/example/example
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examples/asm/trap/trap
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examples/asm/etc/pause
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# Other
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external
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config/deriv
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sim/slack-notifier/slack-webhook-url.txt
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docs/docker/buildroot-config-src
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docs/docker/testvector-generation
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