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			264 lines
		
	
	
		
			6.1 KiB
		
	
	
	
		
			Python
		
	
	
		
			Executable File
		
	
	
	
	
			
		
		
	
	
			264 lines
		
	
	
		
			6.1 KiB
		
	
	
	
		
			Python
		
	
	
		
			Executable File
		
	
	
	
	
| #!/usr/bin/python3
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| ##################################
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| # testgen-CAUSE.py
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| #
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| # dottolia@hmc.edu 1 Mar 2021
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| #
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| # Generate directed and random test vectors for RISC-V Design Validation.
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| ##################################
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| 
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| ##################################
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| # libraries
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| ##################################
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| from datetime import datetime
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| from random import randint 
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| from random import seed
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| from random import getrandbits
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| 
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| ##################################
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| # functions
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| ##################################
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| 
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| #For instruction-fetch access or page-fault exceptions on systems with variable-length instructions, mtval will contain the virtual address of the portion of the instruction that caused the fault while mepc will point to the beginning of the instruction.
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| 
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| def randRegs():
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|   reg1 = randint(1,20)
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|   reg2 = randint(1,20)
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|   reg3 = randint(1,20)
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|   if (reg1 == 6 or reg2 == 6 or reg3 == 6 or reg1 == reg2):
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|     return randRegs()
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|   else:
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|       return str(reg1), str(reg2), str(reg3)
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| 
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| def writeVectors(storecmd):
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|   global testnum
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| 
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|   # Load address misaligned
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|   writeTest(storecmd, f, r, f"""
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|     ecall
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|   """, False, 9)
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|   
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| 
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| def writeTest(storecmd, f, r, test, interrupt, code, resetHander = ""):
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|   global testnum
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|   global testMode
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| 
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|   nops = ""
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|   for i in range(0, randint(1, 16)):
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|     nops+="nop\n"
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| 
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|   lines = f"""
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|     {nops}
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|     li x25, 0xDEADBEA7
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|     auipc x26, 0
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|     addi x26, x26, 8
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|     {test}
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| 
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|     _jend{testnum}:
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| 
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|     {storecmd} x25, 0(x7)
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|     addi x7, x7, {wordsize}
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|   """
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| 
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|   f.write(lines)
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| 
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|   expected = 0
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| 
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|   if (xlen == 32):
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|     line = formatrefstr.format(expected)+"\n"
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|   else:
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|     line = formatrefstr.format(expected % 2**32)+"\n" + formatrefstr.format(expected >> 32) + "\n"
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|   r.write(line)
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|   testnum = testnum+1
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| ##################################
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| # main body
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| ##################################
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| 
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| # change these to suite your tests
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| author = "dottolia@hmc.edu"
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| xlens = [32, 64]
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| numrand = 64;
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| 
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| # setup
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| seed(0x9365DDEB9173AB42) # make tests reproducible
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| 
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| # generate files for each test
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| for xlen in xlens:
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|   formatstrlen = str(int(xlen/4))
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|   formatstr = "0x{:0" + formatstrlen + "x}" # format as xlen-bit hexadecimal number
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|   formatrefstr = "{:08x}" # format as xlen-bit hexadecimal number with no leading 0x
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|   if (xlen == 32):
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|     storecmd = "sw"
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|     wordsize = 4
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|   else:
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|     storecmd = "sd"
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|     wordsize = 8
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| 
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|   corners = [
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|     0x624B3E976C52DD14 % 2**xlen, 2**(xlen-1)-2, 2**(xlen-1)-1, 
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|     2**(xlen-1), 2**(xlen-1)+1, 0xC365DDEB9173AB42 % 2**xlen, 2**(xlen)-2, 2**(xlen)-1
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|   ]
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| 
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|   for testMode in ["m", "s"]:
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|     imperaspath = "../../../imperas-riscv-tests/riscv-test-suite/rv" + str(xlen) + "p/"
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|     basename = "WALLY-" + testMode.upper() + "EPC"
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|     fname = imperaspath + "src/" + basename + ".S"
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|     refname = imperaspath + "references/" + basename + ".reference_output"
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|     testnum = 0
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| 
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|     # print custom header part
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|     f = open(fname, "w")
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|     r = open(refname, "w")
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|     line = "///////////////////////////////////////////\n"
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|     f.write(line)
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|     lines="// "+fname+ "\n// " + author + "\n"
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|     f.write(lines)
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|     line ="// Created " + str(datetime.now()) 
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|     f.write(line)
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| 
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|     # insert generic header
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|     h = open("../testgen_header.S", "r")
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|     for line in h:  
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|       f.write(line)
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| 
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|     # All registers used:
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|     # x30: set to 1 if we should return to & stay in machine mode after trap, 0 otherwise
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|     # ...
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|     # x26: expected epc value
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|     # x25: value to write to memory
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|     # ...
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|     # x19: mtvec old value
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|     # x18: medeleg old value
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|     # x17: sedeleg old value
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| 
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| 
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|     lines = f"""
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|       add x7, x6, x0
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|       csrr x19, mtvec
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| 
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|       csrr x18, medeleg
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|       li x9, {"0b1100000000" if testMode == "s" or testMode == "u" else "0b0000000000"}
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|       csrs medeleg, x9
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| 
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|     """
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| 
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|     if testMode == "u":
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|       lines += f"""
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|         csrr x17, sedeleg
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|         li x9, {"0b1100000000" if testMode == "u" else "0b0000000000"}
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|         csrs sedeleg, x9
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|         """
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| 
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|     lines += f"""
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| 
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|       li x30, 0
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| 
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|       la x1, _j_m_trap
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|       csrw mtvec, x1
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|       la x1, _j_s_trap
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|       csrw stvec, x1
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|       la x1, _j_u_trap
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|       csrw utvec, x1
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|       j _j_t_begin
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| 
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|       _j_m_trap:
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|       csrrs x1, mepc, x0
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|       {"sub x25, x26, x1" if testMode == "m" else "li x25, 0xBAD00003"}
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| 
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|       addi x1, x1, 4
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|       csrrw x0, mepc, x1
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|       bnez x30, _j_all_end
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|       mret
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| 
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|       _j_s_trap:
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|       csrrs x1, sepc, x0
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|       {"sub x25, x26, x1" if testMode == "s" else "li x25, 0xBAD00001"}
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| 
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|       addi x1, x1, 4
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|       csrrw x0, sepc, x1
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|       bnez x30, _j_goto_machine_mode
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|       sret
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| 
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|       _j_u_trap:
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|       csrrs x1, uepc, x0
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|       {"sub x25, x26, x1" if testMode == "u" else "li x25, 0xBAD00000"}
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| 
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|       addi x1, x1, 4
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|       csrrw x0, uepc, x1
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|       bnez x30, _j_goto_supervisor_mode
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|       uret
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| 
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|       _j_goto_supervisor_mode:
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|       csrw sedeleg, x17
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|       j _j_goto_machine_mode
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| 
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|       _j_goto_machine_mode:
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|       csrw medeleg, x18
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|       li x30, 1
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|       ecall
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| 
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|       _j_t_begin:
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|     """
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| 
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|     fromModeOptions = ["m", "s", "u"] if testMode == "m" else (["s", "u"] if testMode == "s" else ["u"])
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| 
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|     f.write(lines)
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| 
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|     for fromMode in fromModeOptions:
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|       lines = ""
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|       
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|       if fromMode == "s" or fromMode == "u":
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|         lines += f"""
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|           li x1, 0b110000000000
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|           csrrc x31, mstatus, x1
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|           li x1, 0b0100000000000
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|           csrrs x31, mstatus, x1
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| 
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|           auipc x1, 0
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|           addi x1, x1, 16 # x1 is now right after the mret instruction
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|           csrw mepc, x1
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|           mret
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| 
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|           # We're now in supervisor mode...
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|         """
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| 
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|       if fromMode == "u":
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|         lines += f"""
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| 
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|         li x1, 0b110000000000
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|         csrrc x31, sstatus, x1
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| 
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|         auipc x1, 0
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|         addi x1, x1, 16 # x1 is now right after the sret instruction
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|         csrw sepc, x1
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|         sret
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| 
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|         # We're now in user mode...
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|         """
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| 
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|       # print directed and random test vectors
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|       f.write(lines)
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|       for i in range(0,numrand):
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|         writeVectors(storecmd)
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| 
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| 
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|     f.write(f"""
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|       li x30, 1
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|       ecall
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|       _j_all_end:
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| 
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|       csrw mtvec, x19
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|     """)
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| 
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|     # print footer
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|     h = open("../testgen_footer.S", "r")
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|     for line in h:  
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|       f.write(line)
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| 
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|     # Finish
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|     lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -1\n"
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|     lines = lines + "\nRV_COMPLIANCE_DATA_END\n" 
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|     f.write(lines)
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|     f.close()
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|     r.close()
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