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32ec457e09
In the dcache we added a register to save the load read data in the event an itlb miss occurs concurrently with the load in the memory stage. Under this situation we need to record the load ReadDataM into a temporary register, SavedReadDataM. At this time the CPU is stall; however the walker is going to change the address in the dcache which destroys this data. When leaving the PTW_READY state via a walker instruction fault or ITLB write we select this SavedReadDataM so that the CPU can capture it.
475 lines
17 KiB
Systemverilog
475 lines
17 KiB
Systemverilog
///////////////////////////////////////////
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// icache.sv
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//
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// Written: ross1728@gmail.com June 04, 2021
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// Modified:
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//
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// Purpose: I Cache controller
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module ICacheCntrl #(parameter BLOCKLEN = 256)
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(
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// Inputs from pipeline
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input logic clk, reset,
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input logic StallF, StallD,
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input logic FlushD,
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// Input the address to read
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// The upper bits of the physical pc
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input logic [`PA_BITS-1:0] PCNextF,
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input logic [`PA_BITS-1:0] PCPF,
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// Signals to/from cache memory
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// The read coming out of it
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input logic [31:0] ICacheMemReadData,
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input logic ICacheMemReadValid,
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// The address at which we want to search the cache memory
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output logic [`PA_BITS-1:0] PCTagF,
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output logic [`PA_BITS-1:0] PCNextIndexF,
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output logic ICacheReadEn,
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// Load data into the cache
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output logic ICacheMemWriteEnable,
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output logic [BLOCKLEN-1:0] ICacheMemWriteData,
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// Outputs to rest of ifu
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// High if the instruction in the fetch stage is compressed
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output logic CompressedF,
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// The instruction that was requested
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// If this instruction is compressed, upper 16 bits may be the next 16 bits or may be zeros
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output logic [31:0] FinalInstrRawF,
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// Outputs to pipeline control stuff
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output logic ICacheStallF, EndFetchState,
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input logic ITLBMissF,
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input logic ITLBWriteF,
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input logic WalkerInstrPageFaultF,
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// Signals to/from ahblite interface
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// A read containing the requested data
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input logic [`XLEN-1:0] InstrInF,
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input logic InstrAckF,
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// The read we request from main memory
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output logic [`PA_BITS-1:0] InstrPAdrF,
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output logic InstrReadF
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);
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// FSM states
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localparam STATE_READY = 'h0;
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localparam STATE_HIT_SPILL = 'h1; // spill, block 0 hit
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localparam STATE_HIT_SPILL_MISS_FETCH_WDV = 'h2; // block 1 miss, issue read to AHB and wait data.
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localparam STATE_HIT_SPILL_MISS_FETCH_DONE = 'h3; // write data into SRAM/LUT
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localparam STATE_HIT_SPILL_MERGE = 'h4; // Read block 0 of CPU access, should be able to optimize into STATE_HIT_SPILL.
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// a challenge is the spill signal gets us out of the ready state and moves us to
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// 1 of the 2 spill branches. However the original fsm design had us return to
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// the ready state when the spill + hits/misses were fully resolved. The problem
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// is the spill signal is based on PCPF so when we return to READY to check if the
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// cache has a hit it still expresses spill. We can fix in 1 of two ways.
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// 1. we can add 1 extra state at the end of each spill branch to returns the instruction
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// to the CPU advancing the CPU and icache to the next instruction.
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// 2. We can assert a signal which is delayed 1 cycle to suppress the spill when we get
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// to the READY state.
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// The first first option is more robust and increases the number of states by 2. The
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// second option is seams like it should work, but I worry there is a hidden interaction
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// between CPU stalling and that register.
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// Picking option 1.
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localparam STATE_HIT_SPILL_FINAL = 'h5; // this state replicates STATE_READY's replay of the
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// spill access but does nto consider spill. It also does not do another operation.
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localparam STATE_MISS_FETCH_WDV = 'h6; // aligned miss, issue read to AHB and wait for data.
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localparam STATE_MISS_FETCH_DONE = 'h7; // write data into SRAM/LUT
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localparam STATE_MISS_READ = 'h8; // read block 1 from SRAM/LUT
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localparam STATE_MISS_SPILL_FETCH_WDV = 'h9; // spill, miss on block 0, issue read to AHB and wait
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localparam STATE_MISS_SPILL_FETCH_DONE = 'ha; // write data into SRAM/LUT
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localparam STATE_MISS_SPILL_READ1 = 'hb; // read block 0 from SRAM/LUT
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localparam STATE_MISS_SPILL_2 = 'hc; // return to ready if hit or do second block update.
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localparam STATE_MISS_SPILL_2_START = 'hd; // return to ready if hit or do second block update.
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localparam STATE_MISS_SPILL_MISS_FETCH_WDV = 'he; // miss on block 1, issue read to AHB and wait
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localparam STATE_MISS_SPILL_MISS_FETCH_DONE = 'hf; // write data to SRAM/LUT
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localparam STATE_MISS_SPILL_MERGE = 'h10; // read block 0 of CPU access,
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localparam STATE_MISS_SPILL_FINAL = 'h11; // this state replicates STATE_READY's replay of the
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// spill access but does nto consider spill. It also does not do another operation.
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localparam STATE_INVALIDATE = 'h12; // *** not sure if invalidate or evict? invalidate by cache block or address?
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localparam STATE_TLB_MISS = 'h13;
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localparam STATE_TLB_MISS_DONE = 'h14;
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localparam AHBByteLength = `XLEN / 8;
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localparam AHBOFFETWIDTH = $clog2(AHBByteLength);
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localparam BlockByteLength = BLOCKLEN / 8;
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localparam OFFSETWIDTH = $clog2(BlockByteLength);
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localparam WORDSPERLINE = BLOCKLEN/`XLEN;
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localparam LOGWPL = $clog2(WORDSPERLINE);
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localparam integer PA_WIDTH = `PA_BITS - 2;
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logic [4:0] CurrState, NextState;
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logic hit, spill;
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logic SavePC;
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logic [1:0] PCMux;
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logic CntReset;
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logic PreCntEn, CntEn;
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logic spillSave;
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logic UnalignedSelect;
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logic FetchCountFlag;
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localparam FetchCountThreshold = WORDSPERLINE - 1;
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logic [LOGWPL-1:0] FetchCount, NextFetchCount;
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logic [`PA_BITS-1:0] PCPreFinalF, PCPSpillF;
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logic [`PA_BITS-1:OFFSETWIDTH] PCPTrunkF;
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logic [15:0] SpillDataBlock0;
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localparam [31:0] NOP = 32'h13;
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logic reset_q;
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logic [1:0] PCMux_q;
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// Misaligned signals
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//logic [`XLEN:0] MisalignedInstrRawF;
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//logic MisalignedStall;
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// Cache fault signals
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//logic FaultStall;
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// on spill we want to get the first 2 bytes of the next cache block.
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// the spill only occurs if the PCPF mod BlockByteLength == -2. Therefore we can
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// simply add 2 to land on the next cache block.
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assign PCPSpillF = PCPF + {{{PA_WIDTH}{1'b0}}, 2'b10}; // *** modelsim does not allow the use of PA_BITS for literal width.
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// now we have to select between these three PCs
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assign PCPreFinalF = PCMux[0] | StallF ? PCPF : PCNextF; // *** don't like the stallf, but it is necessary
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assign PCNextIndexF = PCMux[1] ? PCPSpillF : PCPreFinalF;
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// this mux needs to be delayed 1 cycle as it occurs 1 pipeline stage later.
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// *** read enable may not be necessary.
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flopenr #(2) PCMuxReg(.clk(clk),
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.reset(reset),
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.en(ICacheReadEn),
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.d(PCMux),
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.q(PCMux_q));
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assign PCTagF = PCMux_q[1] ? PCPSpillF : PCPF;
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// truncate the offset from PCPF for memory address generation
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assign PCPTrunkF = PCTagF[`PA_BITS-1:OFFSETWIDTH];
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// Detect if the instruction is compressed
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assign CompressedF = FinalInstrRawF[1:0] != 2'b11;
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// the FSM is always runing, do not stall.
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flopr #(5) stateReg(.clk(clk),
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.reset(reset),
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.d(NextState),
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.q(CurrState));
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assign spill = PCPF[4:1] == 4'b1111 ? 1'b1 : 1'b0;
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assign hit = ICacheMemReadValid; // note ICacheMemReadValid is hit.
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assign FetchCountFlag = (FetchCount == FetchCountThreshold[LOGWPL-1:0]);
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// Next state logic
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always_comb begin
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UnalignedSelect = 1'b0;
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CntReset = 1'b0;
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PreCntEn = 1'b0;
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//InstrReadF = 1'b0;
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ICacheMemWriteEnable = 1'b0;
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spillSave = 1'b0;
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PCMux = 2'b00;
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ICacheReadEn = 1'b0;
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SavePC = 1'b0;
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ICacheStallF = 1'b1;
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case (CurrState)
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STATE_READY: begin
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PCMux = 2'b00;
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ICacheReadEn = 1'b1;
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if (ITLBMissF) begin
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NextState = STATE_TLB_MISS;
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end else if (hit & ~spill) begin
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SavePC = 1'b1;
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ICacheStallF = 1'b0;
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NextState = STATE_READY;
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end else if (hit & spill) begin
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spillSave = 1'b1;
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PCMux = 2'b10;
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NextState = STATE_HIT_SPILL;
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end else if (~hit & ~spill) begin
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CntReset = 1'b1;
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NextState = STATE_MISS_FETCH_WDV;
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end else if (~hit & spill) begin
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CntReset = 1'b1;
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PCMux = 2'b01;
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NextState = STATE_MISS_SPILL_FETCH_WDV;
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end else begin
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NextState = STATE_READY;
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end
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end
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// branch 1, hit spill and 2, miss spill hit
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STATE_HIT_SPILL: begin
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PCMux = 2'b10;
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UnalignedSelect = 1'b1;
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ICacheReadEn = 1'b1;
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if (hit) begin
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NextState = STATE_HIT_SPILL_FINAL;
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end else begin
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CntReset = 1'b1;
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NextState = STATE_HIT_SPILL_MISS_FETCH_WDV;
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end
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end
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STATE_HIT_SPILL_MISS_FETCH_WDV: begin
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PCMux = 2'b10;
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//InstrReadF = 1'b1;
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PreCntEn = 1'b1;
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if (FetchCountFlag & InstrAckF) begin
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NextState = STATE_HIT_SPILL_MISS_FETCH_DONE;
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end else begin
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NextState = STATE_HIT_SPILL_MISS_FETCH_WDV;
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end
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end
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STATE_HIT_SPILL_MISS_FETCH_DONE: begin
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PCMux = 2'b10;
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ICacheMemWriteEnable = 1'b1;
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NextState = STATE_HIT_SPILL_MERGE;
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end
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STATE_HIT_SPILL_MERGE: begin
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PCMux = 2'b10;
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UnalignedSelect = 1'b1;
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ICacheReadEn = 1'b1;
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NextState = STATE_HIT_SPILL_FINAL;
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end
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STATE_HIT_SPILL_FINAL: begin
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ICacheReadEn = 1'b1;
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PCMux = 2'b00;
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UnalignedSelect = 1'b1;
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SavePC = 1'b1;
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NextState = STATE_READY;
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ICacheStallF = 1'b0;
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end
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// branch 3 miss no spill
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STATE_MISS_FETCH_WDV: begin
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PCMux = 2'b01;
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//InstrReadF = 1'b1;
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PreCntEn = 1'b1;
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if (FetchCountFlag & InstrAckF) begin
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NextState = STATE_MISS_FETCH_DONE;
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end else begin
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NextState = STATE_MISS_FETCH_WDV;
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end
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end
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STATE_MISS_FETCH_DONE: begin
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PCMux = 2'b01;
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ICacheMemWriteEnable = 1'b1;
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NextState = STATE_MISS_READ;
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end
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STATE_MISS_READ: begin
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PCMux = 2'b01;
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ICacheReadEn = 1'b1;
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NextState = STATE_READY;
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end
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// branch 4 miss spill hit, and 5 miss spill miss
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STATE_MISS_SPILL_FETCH_WDV: begin
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PCMux = 2'b01;
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PreCntEn = 1'b1;
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//InstrReadF = 1'b1;
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if (FetchCountFlag & InstrAckF) begin
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NextState = STATE_MISS_SPILL_FETCH_DONE;
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end else begin
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NextState = STATE_MISS_SPILL_FETCH_WDV;
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end
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end
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STATE_MISS_SPILL_FETCH_DONE: begin
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PCMux = 2'b01;
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ICacheMemWriteEnable = 1'b1;
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NextState = STATE_MISS_SPILL_READ1;
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end
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STATE_MISS_SPILL_READ1: begin // always be a hit as we just wrote that cache block.
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PCMux = 2'b01; // there is a 1 cycle delay after setting the address before the date arrives.
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ICacheReadEn = 1'b1;
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NextState = STATE_MISS_SPILL_2;
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end
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STATE_MISS_SPILL_2: begin
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PCMux = 2'b10;
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UnalignedSelect = 1'b1;
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spillSave = 1'b1; /// *** Could pipeline these to make it clearer in the fsm.
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ICacheReadEn = 1'b1;
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NextState = STATE_MISS_SPILL_2_START;
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end
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STATE_MISS_SPILL_2_START: begin
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if (~hit) begin
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CntReset = 1'b1;
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NextState = STATE_MISS_SPILL_MISS_FETCH_WDV;
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end else begin
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NextState = STATE_READY;
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ICacheReadEn = 1'b1;
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PCMux = 2'b00;
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UnalignedSelect = 1'b1;
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SavePC = 1'b1;
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ICacheStallF = 1'b0;
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end
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end
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STATE_MISS_SPILL_MISS_FETCH_WDV: begin
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PCMux = 2'b10;
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PreCntEn = 1'b1;
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//InstrReadF = 1'b1;
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if (FetchCountFlag & InstrAckF) begin
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NextState = STATE_MISS_SPILL_MISS_FETCH_DONE;
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end else begin
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NextState = STATE_MISS_SPILL_MISS_FETCH_WDV;
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end
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end
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STATE_MISS_SPILL_MISS_FETCH_DONE: begin
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PCMux = 2'b10;
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ICacheMemWriteEnable = 1'b1;
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NextState = STATE_MISS_SPILL_MERGE;
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end
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STATE_MISS_SPILL_MERGE: begin
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PCMux = 2'b10;
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UnalignedSelect = 1'b1;
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ICacheReadEn = 1'b1;
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NextState = STATE_MISS_SPILL_FINAL;
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end
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STATE_MISS_SPILL_FINAL: begin
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ICacheReadEn = 1'b1;
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PCMux = 2'b00;
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UnalignedSelect = 1'b1;
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SavePC = 1'b1;
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ICacheStallF = 1'b0;
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NextState = STATE_READY;
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end
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STATE_TLB_MISS: begin
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if (WalkerInstrPageFaultF) begin
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NextState = STATE_READY;
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ICacheStallF = 1'b0;
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end else if (ITLBWriteF) begin
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NextState = STATE_TLB_MISS_DONE;
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end else begin
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NextState = STATE_TLB_MISS;
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end
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end
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STATE_TLB_MISS_DONE: begin
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NextState = STATE_READY;
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end
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default: begin
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PCMux = 2'b01;
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NextState = STATE_READY;
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end
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// *** add in error handling and invalidate/evict
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endcase
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end
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assign CntEn = PreCntEn & InstrAckF;
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assign InstrReadF = (CurrState == STATE_HIT_SPILL_MISS_FETCH_WDV) ||
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(CurrState == STATE_MISS_FETCH_WDV) ||
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(CurrState == STATE_MISS_SPILL_FETCH_WDV) ||
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(CurrState == STATE_MISS_SPILL_MISS_FETCH_WDV);
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// to compute the fetch address we need to add the bit shifted
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// counter output to the address.
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flopenr #(LOGWPL)
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FetchCountReg(.clk(clk),
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.reset(reset | CntReset),
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.en(CntEn),
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.d(NextFetchCount),
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.q(FetchCount));
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assign NextFetchCount = FetchCount + 1'b1;
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// This part is confusing.
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// *** Ross Thompson reduce the complexity. This is just dumb.
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// we need to remove the offset bits (PCPTrunkF). Because the AHB interface is XLEN wide
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// we need to address on that number of bits so the PC is extended to the right by AHBByteLength with zeros.
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// fetch count is already aligned to AHBByteLength, but we need to extend back to the full address width with
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// more zeros after the addition. This will be the number of offset bits less the AHBByteLength.
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logic [`PA_BITS-1:OFFSETWIDTH-LOGWPL] PCPTrunkExtF, InstrPAdrTrunkF ;
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assign PCPTrunkExtF = {PCPTrunkF, {{LOGWPL}{1'b0}}};
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// verilator lint_off WIDTH
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assign InstrPAdrTrunkF = PCPTrunkExtF + FetchCount;
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// verilator lint_on WIDTH
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//assign InstrPAdrF = {{PCPTrunkF, {{LOGWPL}{1'b0}}} + FetchCount, {{OFFSETWIDTH-LOGWPL}{1'b0}}};
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assign InstrPAdrF = {InstrPAdrTrunkF, {{OFFSETWIDTH-LOGWPL}{1'b0}}};
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// store read data from memory interface before writing into SRAM.
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genvar i;
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generate
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for (i = 0; i < WORDSPERLINE; i++) begin:storebuffer
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flopenr #(`XLEN) sb(.clk(clk),
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.reset(reset),
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.en(InstrAckF & (i == FetchCount)),
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.d(InstrInF),
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.q(ICacheMemWriteData[(i+1)*`XLEN-1:i*`XLEN]));
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end
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endgenerate
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// what address is used to write the SRAM?
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// spills require storing the first cache block so it can merged
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// with the second
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// can optimize size, for now just make it the size of the data
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// leaving the cache memory.
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flopenr #(16) SpillInstrReg(.clk(clk),
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.en(spillSave),
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.reset(reset),
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.d(ICacheMemReadData[15:0]),
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.q(SpillDataBlock0));
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|
|
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// use the not quite final PC to do the final selection.
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logic [1:1] PCPreFinalF_q;
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flopenr #(1) PCFReg(.clk(clk),
|
|
.reset(reset),
|
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.en(~StallF),
|
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.d(PCPreFinalF[1]),
|
|
.q(PCPreFinalF_q[1]));
|
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assign FinalInstrRawF = spill ? {ICacheMemReadData[15:0], SpillDataBlock0} : ICacheMemReadData;
|
|
|
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// There is a frustrating issue on the first access.
|
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// The cache will not contain any valid data but will contain x's on
|
|
// reset. This makes FinalInstrRawF invalid. On the first cycle out of
|
|
// reset this register will pickup this x and it will propagate throughout
|
|
// the cpu causing simulation failure, most likely a trap for invalid instruction.
|
|
// Reset must be held 1 cycle longer to prevent this issue. additionally the
|
|
// reset should be to a NOP rather than 0.
|
|
|
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// register reset
|
|
flop #(1) resetReg (.clk(clk),
|
|
.d(reset),
|
|
.q(reset_q));
|
|
|
|
|
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endmodule
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