mirror of
https://github.com/openhwgroup/cvw
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49 lines
1.4 KiB
Plaintext
49 lines
1.4 KiB
Plaintext
# wally.do
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# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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#
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# Modification by Oklahoma State University & Harvey Mudd College
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# Use with Testbench
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# James Stine, 2008; David Harris 2021
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# Go Cowboys!!!!!!
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#
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# Takes 1:10 to run RV64IC tests using gui
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onbreak {resume}
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# create library
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if [file exists work] {
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vdel -all
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}
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vlib work
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# compile source files
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# suppress spurious warnngs about
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# "Extra checking for conflicts with always_comb done at vopt time"
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# because vsim will run vopt
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# start and run simulation
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# remove +acc flag for faster sim during regressions if there is no need to access internal signals
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# *** modelsim won't take `PA_BITS, but will take other defines for the lengths of DTIM_RANGE and IROM_LEN. For now just live with the warnings.
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vlog +incdir+../config/$1 \
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+incdir+../config/shared \
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../../external/ImperasDV-HMC/Imperas/ImpPublic/source/host/rvvi/rvviTrace.sv \
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../src/cvw.sv \
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../testbench/testbench_imperas.sv \
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../testbench/common/*.sv \
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../src/*/*.sv \
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../src/*/*/*.sv \
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-suppress 2583 \
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-suppress 7063
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vopt +acc work.testbench -G DEBUG=1 -o workopt
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eval vsim workopt +nowarn3829 -fatal 7 \
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+testDir=$env(TESTDIR) $env(OTHERFLAGS)
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view wave
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#-- display input and output signals as hexidecimal values
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add log -recursive /*
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do wave.do
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run -all
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noview ../testbench/testbench_imperas.sv
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view wave
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