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https://github.com/openhwgroup/cvw
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2f2a4f4500
Loading buildroot at 483M instructions started with a spill + ITLBMiss. The spillsupport logic allowed transition to the second access only after the bus/cache completed the first operation. However the BusStall was suppressed if ITLBMissF occurs resulting in the spillfsm advancing to the second operation. Now the spill logic also takes in ITLBMissF and prevents the early transition to the second access.
318 lines
15 KiB
Systemverilog
318 lines
15 KiB
Systemverilog
///////////////////////////////////////////
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// ifu.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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//
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// Purpose: Instrunction Fetch Unit
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// PC, branch prediction, instruction cache
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module ifu (
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input logic clk, reset,
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input logic StallF, StallD, StallE, StallM, StallW,
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input logic FlushF, FlushD, FlushE, FlushM, FlushW,
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// Bus interface
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(* mark_debug = "true" *) input logic [`XLEN-1:0] IFUBusHRDATA,
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(* mark_debug = "true" *) input logic IFUBusAck,
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(* mark_debug = "true" *) output logic [`PA_BITS-1:0] IFUBusAdr,
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(* mark_debug = "true" *) output logic IFUBusRead,
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(* mark_debug = "true" *) output logic IFUStallF,
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(* mark_debug = "true" *) output logic [`XLEN-1:0] PCF,
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// Execute
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output logic [`XLEN-1:0] PCLinkE,
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input logic PCSrcE,
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input logic [`XLEN-1:0] IEUAdrE,
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output logic [`XLEN-1:0] PCE,
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output logic BPPredWrongE,
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// Mem
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input logic RetM, TrapM,
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input logic [`XLEN-1:0] PrivilegedNextPCM,
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input logic InvalidateICacheM,
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output logic [31:0] InstrD, InstrM,
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output logic [`XLEN-1:0] PCM,
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// branch predictor
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output logic [4:0] InstrClassM,
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output logic BPPredDirWrongM,
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output logic BTBPredPCWrongM,
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output logic RASPredPCWrongM,
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output logic BPPredClassNonCFIWrongM,
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// Faults
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input logic IllegalBaseInstrFaultD,
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output logic InstrPageFaultF,
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output logic IllegalIEUInstrFaultD,
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output logic InstrMisalignedFaultM,
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output logic [`XLEN-1:0] InstrMisalignedAdrM,
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input logic ExceptionM, PendingInterruptM,
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// mmu management
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input logic [1:0] PrivilegeModeW,
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input logic [`XLEN-1:0] PTE,
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input logic [1:0] PageType,
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input logic [`XLEN-1:0] SATP_REGW,
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input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV,
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input logic [1:0] STATUS_MPP,
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input logic ITLBWriteF, ITLBFlushF,
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output logic ITLBMissF,
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// pmp/pma (inside mmu) signals. *** temporarily from AHB bus but eventually replace with internal versions pre H
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input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],
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input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0],
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output logic InstrAccessFaultF,
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output logic ICacheAccess,
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output logic ICacheMiss
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);
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(* mark_debug = "true" *) logic [`XLEN-1:0] PCCorrectE, UnalignedPCNextF, PCNextF;
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logic BranchMisalignedFaultE;
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logic PrivilegedChangePCM;
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logic IllegalCompInstrD;
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logic [`XLEN-1:0] PCPlus2or4F, PCLinkD;
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logic [`XLEN-3:0] PCPlusUpperF;
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logic CompressedF;
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logic [31:0] InstrRawD, InstrRawF;
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logic [31:0] FinalInstrRawF;
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logic [31:0] InstrE;
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logic [`XLEN-1:0] PCD;
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localparam [31:0] nop = 32'h00000013; // instruction for NOP
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logic [`XLEN-1:0] PCBPWrongInvalidate;
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(* mark_debug = "true" *) logic [`PA_BITS-1:0] PCPF; // used to either truncate or expand PCPF and PCNextF into `PA_BITS width.
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logic [`XLEN+1:0] PCFExt;
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logic CacheableF;
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logic [`XLEN-1:0] PCNextFSpill;
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logic [`XLEN-1:0] PCFSpill;
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logic SelNextSpillF;
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logic ICacheFetchLine;
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logic BusStall;
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logic ICacheStallF, IFUCacheBusStallF;
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logic CPUBusy;
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(* mark_debug = "true" *) logic [31:0] PostSpillInstrRawF;
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// branch predictor signal
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logic [`XLEN-1:0] PCNext1F, PCNext2F, PCNext0F;
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assign PCFExt = {2'b00, PCFSpill};
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Spill Support *** add other banners
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/////////////////////////////////////////////////////////////////////////////////////////////
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if(`C_SUPPORTED) begin : SpillSupport
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spillsupport spillsupport(.clk, .reset, .StallF, .PCF, .PCPlusUpperF, .PCNextF, .InstrRawF,
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.IFUCacheBusStallF, .ITLBMissF, .PCNextFSpill, .PCFSpill,
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.SelNextSpillF, .PostSpillInstrRawF, .CompressedF);
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end else begin : NoSpillSupport
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assign PCNextFSpill = PCNextF;
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assign PCFSpill = PCF;
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assign PostSpillInstrRawF = InstrRawF;
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assign {SelNextSpillF, CompressedF} = 0;
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end
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////////////////////////////////////////////////////////////////////////////////////////////////
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// Memory management
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////////////////////////////////////////////////////////////////////////////////////////////////
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if(`ZICSR_SUPPORTED == 1) begin : immu
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mmu #(.TLB_ENTRIES(`ITLB_ENTRIES), .IMMU(1))
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immu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
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.PrivilegeModeW, .DisableTranslation(1'b0),
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.PAdr(PCFExt[`PA_BITS-1:0]),
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.VAdr(PCFSpill),
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.Size(2'b10),
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.PTE(PTE),
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.PageTypeWriteVal(PageType),
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.TLBWrite(ITLBWriteF),
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.TLBFlush(ITLBFlushF),
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.PhysicalAddress(PCPF),
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.TLBMiss(ITLBMissF),
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.Cacheable(CacheableF), .Idempotent(), .AtomicAllowed(),
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.InstrAccessFaultF, .LoadAccessFaultM(), .StoreAmoAccessFaultM(),
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.InstrPageFaultF, .LoadPageFaultM(), .StoreAmoPageFaultM(),
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.LoadMisalignedFaultM(), .StoreAmoMisalignedFaultM(),
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.AtomicAccessM(1'b0),.ExecuteAccessF(1'b1), .WriteAccessM(1'b0), .ReadAccessM(1'b0),
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.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW);
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end else begin
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assign {ITLBMissF, InstrAccessFaultF, InstrPageFaultF} = '0;
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assign PCPF = PCFExt[`PA_BITS-1:0];
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assign CacheableF = '1;
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end
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////////////////////////////////////////////////////////////////////////////////////////////////
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// Memory
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////////////////////////////////////////////////////////////////////////////////////////////////
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logic [`XLEN-1:0] AllInstrRawF;
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assign InstrRawF = AllInstrRawF[31:0];
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if (`IMEM == `MEM_TIM) begin : irom // *** fix up dtim taking PA_BITS rather than XLEN, *** IEUAdr is a bad name. Probably use a ROM rather than DTIM
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dtim irom(.clk, .reset, .CPUBusy, .LSURWM(2'b10), .IEUAdrM(PCPF[31:0]), .IEUAdrE(PCNextFSpill),
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.TrapM(1'b0), .FinalWriteDataM(),
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.ReadDataWordM(AllInstrRawF), .BusStall, .LSUBusWrite(), .LSUBusRead(IFUBusRead),
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.BusCommittedM(), .ReadDataWordMuxM(), .DCacheStallM(ICacheStallF),
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.DCacheCommittedM(), .DCacheMiss(ICacheMiss), .DCacheAccess(ICacheAccess));
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end else begin : bus
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localparam integer WORDSPERLINE = (`IMEM == `MEM_CACHE) ? `ICACHE_LINELENINBITS/`XLEN : 1;
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localparam integer LINELEN = (`IMEM == `MEM_CACHE) ? `ICACHE_LINELENINBITS : `XLEN;
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localparam integer LOGWPL = (`DMEM == `MEM_CACHE) ? $clog2(WORDSPERLINE) : 1;
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logic [LINELEN-1:0] ReadDataLine;
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logic [LINELEN-1:0] ICacheMemWriteData;
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logic [`PA_BITS-1:0] ICacheBusAdr;
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logic ICacheBusAck;
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logic save,restore;
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logic [31:0] temp;
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busdp #(WORDSPERLINE, LINELEN, 32, LOGWPL)
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busdp(.clk, .reset,
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.LSUBusHRDATA(IFUBusHRDATA), .LSUBusAck(IFUBusAck), .LSUBusWrite(), .LSUBusWriteCrit(),
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.LSUBusRead(IFUBusRead), .LSUBusSize(),
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.LSUFunct3M(3'b010), .LSUBusAdr(IFUBusAdr), .DCacheBusAdr(ICacheBusAdr),
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.WordCount(), .LSUBusHWDATA(),
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.DCacheFetchLine(ICacheFetchLine),
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.DCacheWriteLine(1'b0), .DCacheBusAck(ICacheBusAck),
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.DCacheMemWriteData(ICacheMemWriteData), .LSUPAdrM(PCPF),
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.FinalAMOWriteDataM(), .ReadDataWordM(FinalInstrRawF), .ReadDataWordMuxM(AllInstrRawF[31:0]),
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.IgnoreRequest(ITLBMissF), .LSURWM(2'b10), .CPUBusy, .CacheableM(CacheableF),
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.BusStall, .BusCommittedM());
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if(`IMEM == `MEM_CACHE) begin : icache
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logic [1:0] IFURWF;
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assign IFURWF = CacheableF ? 2'b10 : 2'b00;
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cache #(.LINELEN(`ICACHE_LINELENINBITS),
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.NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS),
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.NUMWAYS(`ICACHE_NUMWAYS), .DCACHE(0))
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icache(.clk, .reset, .CPUBusy, .IgnoreRequestTLB(ITLBMissF), .IgnoreRequestTrapM('0),
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.CacheMemWriteData(ICacheMemWriteData), .CacheBusAck(ICacheBusAck),
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.CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF),
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.CacheFetchLine(ICacheFetchLine),
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.CacheWriteLine(), .ReadDataLine(ReadDataLine),
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.save, .restore,
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.CacheMiss(ICacheMiss), .CacheAccess(ICacheAccess),
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.FinalWriteData('0),
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.RW(IFURWF),
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.Atomic('0), .FlushCache('0),
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.NextAdr(PCNextFSpill[11:0]),
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.PAdr(PCPF),
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.CacheCommitted(), .InvalidateCacheM(InvalidateICacheM));
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subcachelineread #(LINELEN, 32, 16) subcachelineread(
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.clk, .reset, .PAdr(PCPF), .save, .restore,
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.ReadDataLine, .ReadDataWord(FinalInstrRawF));
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end else begin : passthrough
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assign {ICacheFetchLine, ICacheBusAdr, ICacheStallF, FinalInstrRawF} = '0;
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assign ICacheAccess = CacheableF; assign ICacheMiss = CacheableF;
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end
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end
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assign IFUCacheBusStallF = ICacheStallF | BusStall;
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assign IFUStallF = IFUCacheBusStallF | SelNextSpillF;
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assign CPUBusy = StallF & ~SelNextSpillF;
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flopenl #(32) AlignedInstrRawDFlop(clk, reset, ~StallD, FlushD ? nop : PostSpillInstrRawF, nop, InstrRawD);
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assign PrivilegedChangePCM = RetM | TrapM;
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mux2 #(`XLEN) pcmux1(.d0(PCNext0F), .d1(PCCorrectE), .s(BPPredWrongE), .y(PCNext1F));
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mux2 #(`XLEN) pcmux2(.d0(PCNext1F), .d1(PCBPWrongInvalidate), .s(InvalidateICacheM), .y(PCNext2F));
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mux2 #(`XLEN) pcmux3(.d0(PCNext2F), .d1(PrivilegedNextPCM), .s(PrivilegedChangePCM), .y(UnalignedPCNextF));
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assign PCNextF = {UnalignedPCNextF[`XLEN-1:1], 1'b0}; // hart-SPEC p. 21 about 16-bit alignment
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flopenl #(`XLEN) pcreg(clk, reset, ~StallF, PCNextF, `RESET_VECTOR, PCF);
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// branch and jump predictor
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if (`BPRED_ENABLED) begin : bpred
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logic BPPredWrongM;
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logic SelBPPredF;
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logic [`XLEN-1:0] BPPredPCF;
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bpred bpred(.clk, .reset,
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.StallF, .StallD, .StallE, .StallM,
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.FlushF, .FlushD, .FlushE, .FlushM,
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.InstrD, .PCNextF, .BPPredPCF, .SelBPPredF, .PCE, .PCSrcE, .IEUAdrE,
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.PCD, .PCLinkE, .InstrClassM, .BPPredWrongE, .BPPredWrongM,
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.BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM);
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mux2 #(`XLEN) pcmux0(.d0(PCPlus2or4F), .d1(BPPredPCF), .s(SelBPPredF), .y(PCNext0F));
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// Mux only required on instruction class miss prediction.
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mux2 #(`XLEN) pcmuxBPWrongInvalidateFlush(.d0(PCE), .d1(PCF),
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.s(BPPredWrongM), .y(PCBPWrongInvalidate));
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mux2 #(`XLEN) pccorrectemux(.d0(PCLinkE), .d1(IEUAdrE), .s(PCSrcE), .y(PCCorrectE));
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end else begin : bpred
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assign BPPredWrongE = PCSrcE;
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assign {BPPredDirWrongM, BTBPredPCWrongM, RASPredPCWrongM, BPPredClassNonCFIWrongM} = '0;
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assign PCNext0F = PCPlus2or4F;
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assign PCCorrectE = IEUAdrE;
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assign PCBPWrongInvalidate = PCE;
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end
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// pcadder
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// add 2 or 4 to the PC, based on whether the instruction is 16 bits or 32
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assign PCPlusUpperF = PCF[`XLEN-1:2] + 1; // add 4 to PC
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// choose PC+2 or PC+4 based on CompressedF, which arrives later.
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// Speeds up critical path as compared to selecting adder input based on CompressedF
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always_comb
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if (CompressedF) // add 2
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if (PCF[1]) PCPlus2or4F = {PCPlusUpperF, 2'b00};
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else PCPlus2or4F = {PCF[`XLEN-1:2], 2'b10};
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else PCPlus2or4F = {PCPlusUpperF, PCF[1:0]}; // add 4
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// Decode stage pipeline register and logic
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flopenrc #(`XLEN) PCDReg(clk, reset, FlushD, ~StallD, PCF, PCD);
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// expand 16-bit compressed instructions to 32 bits
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decompress decomp(.InstrRawD, .InstrD, .IllegalCompInstrD);
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assign IllegalIEUInstrFaultD = IllegalBaseInstrFaultD | IllegalCompInstrD; // illegal if bad 32 or 16-bit instr
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// Misaligned PC logic
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// Instruction address misalignement only from br/jal(r) instructions.
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// instruction address misalignment is generated by the target of control flow instructions, not
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// the fetch itself.
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// xret and Traps both cannot produce instruction misaligned.
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// xret: mepc is an MXLEN-bit read/write register formatted as shown in Figure 3.21.
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// The low bit of mepc (mepc[0]) is always zero. On implementations that support
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// only IALIGN=32, the two low bits (mepc[1:0]) are always zero.
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// Spec 3.1.14
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// Traps: Can’t happen. The bottom two bits of MTVEC are ignored so the trap always is to a multiple of 4. See 3.1.7 of the privileged spec.
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assign BranchMisalignedFaultE = (IEUAdrE[1] & ~`C_SUPPORTED) & PCSrcE;
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flopenr #(1) InstrMisalginedReg(clk, reset, ~StallM, BranchMisalignedFaultE, InstrMisalignedFaultM);
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flopenr #(`XLEN) InstrMisalignedAdrReg(clk, reset, ~StallM, PCNextF, InstrMisalignedAdrM);
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// Instruction and PC/PCLink pipeline registers
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flopenr #(32) InstrEReg(clk, reset, ~StallE, FlushE ? nop : InstrD, InstrE);
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flopenr #(32) InstrMReg(clk, reset, ~StallM, FlushM ? nop : InstrE, InstrM);
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flopenr #(`XLEN) PCEReg(clk, reset, ~StallE, PCD, PCE);
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flopenr #(`XLEN) PCMReg(clk, reset, ~StallM, PCE, PCM);
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flopenr #(`XLEN) PCPDReg(clk, reset, ~StallD, PCPlus2or4F, PCLinkD);
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flopenr #(`XLEN) PCPEReg(clk, reset, ~StallE, PCLinkD, PCLinkE);
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endmodule
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