mirror of
https://github.com/openhwgroup/cvw
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244 lines
9.2 KiB
Python
Executable File
244 lines
9.2 KiB
Python
Executable File
#! /usr/bin/python3
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import sys, fileinput, re
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# Ross Thompson
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# July 27, 2021
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# Rewrite of the linux trace parser.
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InstrStartDelim = '=>'
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InstrEndDelim = '-----'
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#InputFile = 'noparse.txt'
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#InputFile = sys.stdin
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#InputFile = 'temp.txt'
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#OutputFile = 'parsedAll.txt'
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HUMAN_READABLE = False
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def toDict(lst):
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'Converts the list of register values to a dictionary'
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dct= {}
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for item in lst:
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regTup = item.split()
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dct[regTup[0]] = int(regTup[2], 10)
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del dct['pc']
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return dct
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def whichClass(text, Regs):
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'Which instruction class?'
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#print(text, Regs)
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if text[0:2] == 'ld' or text[0:2] == 'lw' or text[0:2] == 'lh' or text[0:2] == 'lb':
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return ('load', WhatAddr(text, Regs), None, WhatMemDestSource(text))
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elif text[0:2] == 'sd' or text[0:2] == 'sw' or text[0:2] == 'sh' or text[0:2] == 'sb':
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return ('store', WhatAddr(text, Regs), WhatMemDestSource(text), None)
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elif text[0:3] == 'amo':
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return ('amo', WhatAddrAMO(text, Regs), WhatMemDestSource(text), WhatMemDestSource(text))
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elif text[0:2] == 'lr':
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return ('lr', WhatAddrLR(text, Regs), None, WhatMemDestSource(text))
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elif text[0:2] == 'sc':
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return ('sc', WhatAddrSC(text, Regs), WhatMemDestSource(text), None)
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else:
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return ('other', None, None, None)
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def whatChanged(dct0, dct1):
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'Compares two dictionaries of instrution registers and indicates which registers changed'
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dct = {}
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for key in dct0:
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if (dct1[key] != dct0[key]):
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dct[key] = dct1[key]
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return dct
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def WhatMemDestSource(text):
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''''What is the destination register. Used to compute where the read data is
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on a load or the write data on a store.'''
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return text.split()[1].split(',')[0]
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def WhatAddr(text, Regs):
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'What is the data memory address?'
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Imm = text.split(',')[1]
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(Imm, Src) = Imm.split('(')
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Imm = int(Imm.strip(), 10)
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Src = Src.strip(')').strip()
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RegVal = Regs[Src]
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return Imm + RegVal
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def WhatAddrAMO(text, Regs):
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'What is the data memory address?'
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Src = text.split('(')[1]
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Src = Src.strip(')').strip()
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return Regs[Src]
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def WhatAddrLR(text, Regs):
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'What is the data memory address?'
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Src = text.split('(')[1]
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Src = Src.strip(')').strip()
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return Regs[Src]
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def WhatAddrSC(text, Regs):
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'What is the data memory address?'
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Src = text.split('(')[1]
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Src = Src.strip(')').strip()
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return Regs[Src]
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def PrintInstr(instr):
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if instr[2] == None:
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return
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ChangedRegisters = instr[4]
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GPR = ''
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CSR = []
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for key in ChangedRegisters:
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# filter out csr which are not checked.
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if(key in RegNumber):
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if(RegNumber[key] < 32):
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# GPR
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if(HUMAN_READABLE):
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GPR = '{:-2d} {:016x}'.format(RegNumber[key], ChangedRegisters[key])
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else:
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GPR = '{:d} {:x}'.format(RegNumber[key], ChangedRegisters[key])
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else:
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if(HUMAN_READABLE):
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CSR.extend([key, '{:016x}'.format(ChangedRegisters[key])])
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else:
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CSR.extend([key, '{:x}'.format(ChangedRegisters[key])])
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CSRStr = ' '.join(CSR)
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#print(instr)
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if (HUMAN_READABLE == True):
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outString='{:016x} {:08x} {:25s}'.format(instr[0], instr[1], instr[2])
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if(len(GPR) != 0):
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outString+=' GPR {}'.format(GPR)
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if(instr[3] == 'load' or instr[3] == 'lr'):
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outString+=' MemR {:016x} {:016x} {:016x}'.format(instr[5], 0, instr[7])
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if(instr[3] == 'store'):
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outString+='\t\t\t MemW {:016x} {:016x} {:016x}'.format(instr[5], instr[6], 0)
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if(len(CSR) != 0):
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outString+=' CSR {}'.format(CSRStr)
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else:
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outString='{:x} {:x} {:s}'.format(instr[0], instr[1], instr[2].replace(' ', '_'))
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if(len(GPR) != 0):
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outString+=' GPR {}'.format(GPR)
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if(instr[3] == 'load' or instr[3] == 'lr'):
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outString+=' MemR {:x} {:x} {:x}'.format(instr[5], 0, instr[7])
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if(instr[3] == 'store'):
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outString+=' MemW {:x} {:x} {:x}'.format(instr[5], instr[6], 0)
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if(len(CSR) != 0):
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outString+=' CSR {}'.format(CSRStr)
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outString+='\n'
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return outString
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# =========
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# Main Code
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# =========
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# Parse argument for interrupt file
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if len(sys.argv) != 2:
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sys.exit('Error parseGDBtoTrace.py expects 1 arg:\n <interrupt filename>>')
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interruptFname = sys.argv[1]
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# reg number
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RegNumber = {'zero': 0, 'ra': 1, 'sp': 2, 'gp': 3, 'tp': 4, 't0': 5, 't1': 6, 't2': 7, 's0': 8, 's1': 9, 'a0': 10, 'a1': 11, 'a2': 12, 'a3': 13, 'a4': 14, 'a5': 15, 'a6': 16, 'a7': 17, 's2': 18, 's3': 19, 's4': 20, 's5': 21, 's6': 22, 's7': 23, 's8': 24, 's9': 25, 's10': 26, 's11': 27, 't3': 28, 't4': 29, 't5': 30, 't6': 31, 'mhartid': 32, 'mstatus': 33, 'mip': 34, 'mie': 35, 'mideleg': 36, 'medeleg': 37, 'mtvec': 38, 'stvec': 39, 'mepc': 40, 'sepc': 41, 'mcause': 42, 'scause': 43, 'mtval': 44, 'stval': 45, 'mscratch': 46, 'sscratch': 47, 'satp': 48}
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# initial state
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CurrentInstr = ['0', '0', None, 'other', {'zero': 0, 'ra': 0, 'sp': 0, 'gp': 0, 'tp': 0, 't0': 0, 't1': 0, 't2': 0, 's0': 0, 's1': 0, 'a0': 0, 'a1': 0, 'a2': 0, 'a3': 0, 'a4': 0, 'a5': 0, 'a6': 0, 'a7': 0, 's2': 0, 's3': 0, 's4': 0, 's5': 0, 's6': 0, 's7': 0, 's8': 0, 's9': 0, 's10': 0, 's11': 0, 't3': 0, 't4': 0, 't5': 0, 't6': 0, 'mhartid': 0, 'mstatus': 0, 'mip': 0, 'mie': 0, 'mideleg': 0, 'medeleg': 0, 'mtvec': 0, 'stvec': 0, 'mepc': 0, 'sepc': 0, 'mcause': 0, 'scause': 0, 'mtval': 0, 'stval': 0, 'mscratch': 0, 'sscratch': 0, 'satp': 0}, {}, None, None, None]
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#with open (InputFile, 'r') as InputFileFP:
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#lines = InputFileFP.readlines()
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lineNum = 0
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StartLine = 0
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EndLine = 0
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numInstrs = 0
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#instructions = []
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MemAdr = 0
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lines = []
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interrupts=open(interruptFname,'w')
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interrupts.close()
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prevInstrOutString=''
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currInstrOutString=''
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for line in fileinput.input('-'):
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if line.startswith('riscv_cpu_do_interrupt'):
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with open(interruptFname,'a') as interrupts:
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# Write line
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# Example line: hart:0, async:0, cause:0000000000000002, epc:0x0000000080008548, tval:0x0000000000000000, desc=illegal_instruction
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interrupts.write(line)
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# Write instruction count
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interrupts.write(str(numInstrs)+'\n')
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# Convert line to rows of info for easier Verilog parsing
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vals=line.strip('riscv_cpu_do_interrupt: ').strip('\n').split(',')
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vals=[val.split(':')[-1].strip(' ') for val in vals]
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vals=[val.split('=')[-1].strip(' ') for val in vals]
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for val in vals:
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interrupts.write(val+'\n')
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continue
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lines.insert(lineNum, line)
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if InstrStartDelim in line:
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lineNum = 0
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StartLine = lineNum
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elif InstrEndDelim in line:
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EndLine = lineNum
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(InstrBits, text) = lines[StartLine].split(':')
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InstrBits = int(InstrBits.strip('=> '), 16)
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text = text.strip()
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PC = int(lines[StartLine+1].split(':')[0][2:], 16)
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Regs = toDict(lines[StartLine+2:EndLine])
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(Class, Addr, WriteReg, ReadReg) = whichClass(text, Regs)
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#print("CWR", Class, WriteReg, ReadReg)
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PreviousInstr = CurrentInstr
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Changed = whatChanged(PreviousInstr[4], Regs)
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if (ReadReg !=None): ReadData = ReadReg
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else: ReadData = None
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if (WriteReg !=None): WriteData = WriteReg
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else: WriteData = None
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CurrentInstr = [PC, InstrBits, text, Class, Regs, Changed, Addr, WriteData, ReadData]
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#print(CurrentInstr[0:4], PreviousInstr[5], CurrentInstr[6:7], PreviousInstr[8])
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# pc, instrbits, text and class come from the last line.
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MoveInstrToRegWriteLst = PreviousInstr[0:4]
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# updated registers come from the current line.
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MoveInstrToRegWriteLst.append(CurrentInstr[5]) # destination regs
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# memory address if present comes from the last line.
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MoveInstrToRegWriteLst.append(PreviousInstr[6]) # MemAdrM
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# write data from the previous line
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#MoveInstrToRegWriteLst.append(PreviousInstr[7]) # WriteDataM
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if (PreviousInstr[7] != None):
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MoveInstrToRegWriteLst.append(Regs[PreviousInstr[7]]) # WriteDataM
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else:
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MoveInstrToRegWriteLst.append(None)
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# read data from the current line
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#MoveInstrToRegWriteLst.append(PreviousInstr[8]) # ReadDataM
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if (PreviousInstr[8] != None):
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MoveInstrToRegWriteLst.append(Regs[PreviousInstr[8]]) # ReadDataM
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else:
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MoveInstrToRegWriteLst.append(None)
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lines.clear()
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#instructions.append(MoveInstrToRegWriteLst)
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prevInstrOutString = currInstrOutString
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currInstrOutString = PrintInstr(MoveInstrToRegWriteLst)
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# Remove duplicates
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if (PreviousInstr[0] != CurrentInstr[0]) and (currInstrOutString != None):
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sys.stdout.write(currInstrOutString)
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numInstrs += 1
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if (numInstrs % 1e5 == 0):
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sys.stderr.write('GDB trace parser reached '+str(numInstrs/1.0e6)+' million instrs.\n')
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sys.stderr.flush()
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lineNum += 1
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#for instruction in instructions[1::]:
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#with open(OutputFile, 'w') as OutputFileFP:
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# print('opened file')
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