mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
| .. | ||
| ahbsdc@33418c8dc1 | ||
| branch-predictor-simulator@3e424e902f | ||
| coremark@f3e8f2e094 | ||
| cvw-arch-verif@80cdee231f | ||
| embench-iot@54fd9a0f10 | ||
| FreeRTOS-Kernel@17a46c252f | ||
| riscv-arch-test@7152865aca | ||
| riscv-dv@f0c570d112 | ||
| riscvISACOV@ac9fa2d386 | ||
| SoftFloat-3e | ||
| TestFloat-3e | ||
| verilog-ethernet@c180b22ed5 | ||
| vivado-boards@e5f0728cd2 | ||
| README.md | ||
| sparse-checkout | ||
verilog-ethernet contains many ethernet devices. Wally's synthesizable RVVI interface only requires a small subset of these files. To do a sparse checkout of this repo copy sparse-checkout to cvw/.git/modules/addins/verilog-ethernet/info This will make the working directory only contain the necessary files.