Ross Thompson b3849d8abb Moved data path logic from icacheCntrl to icache.		2021-08-26 10:58:19 -05:00
..
cache-sram.sv	A few more cache fixes	2021-04-13 01:07:40 -04:00
cachereplacementpolicy.sv	Forgot to include a few files in the last few commits.	2021-08-25 22:30:05 -05:00
cacheway.sv	Moved LRU and storage for the LRU into a single module. Also found a subtle bug with the update address used to write the cache's memory.	2021-08-25 21:09:42 -05:00
dcache_ptw_interaction_README.txt	Added documentation about how the dcache and ptw interact.	2021-08-12 18:05:36 -05:00
dcache.sv	Forgot to include a few files in the last few commits.	2021-08-25 22:30:05 -05:00
dcachefsm.sv	Forgot to include a few files in the last few commits.	2021-08-25 22:30:05 -05:00
dmapped.sv	Gave names to for loops in generate blocks for ease of reference	2021-07-04 18:52:16 -04:00
icache.sv	Moved data path logic from icacheCntrl to icache.	2021-08-26 10:58:19 -05:00
ICacheCntrl.sv	Moved data path logic from icacheCntrl to icache.	2021-08-26 10:58:19 -05:00
ICacheMem.sv	Partial implementation of the data cache. Missing the fsm.	2021-07-07 17:52:16 -05:00
sram1rw.sv	change sram1rw to have a small delay so that we don't have signals changing on clock edges	2021-07-19 11:30:07 -04:00