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85 lines
2.7 KiB
Systemverilog
85 lines
2.7 KiB
Systemverilog
///////////////////////////////////////////
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// fdivsqrtstage2.sv
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//
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// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu
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// Modified:13 January 2022
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//
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// Purpose: radix-2 divsqrt recurrence stage
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//
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// Documentation: RISC-V System on Chip Design Chapter 13
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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/* verilator lint_off UNOPTFLAT */
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module fdivsqrtstage2 (
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input logic [`DIVb+3:0] D, DBar,
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input logic [`DIVb:0] U, UM,
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input logic [`DIVb+3:0] WS, WC,
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input logic [`DIVb+1:0] C,
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input logic SqrtE,
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output logic un,
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output logic [`DIVb+1:0] CNext,
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output logic [`DIVb:0] UNext, UMNext,
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output logic [`DIVb+3:0] WSNext, WCNext
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);
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/* verilator lint_on UNOPTFLAT */
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logic [`DIVb+3:0] Dsel;
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logic up, uz;
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logic [`DIVb+3:0] F;
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logic [`DIVb+3:0] AddIn;
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logic [`DIVb+3:0] WSA, WCA;
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// Qmient Selection logic
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// Given partial remainder, select digit of +1, 0, or -1 (up, uz, un)
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// q encoding:
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// 1000 = +2
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// 0100 = +1
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// 0000 = 0
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// 0010 = -1
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// 0001 = -2
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fdivsqrtqsel2 qsel2(WS[`DIVb+3:`DIVb], WC[`DIVb+3:`DIVb], up, uz, un);
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// Sqrt F generation. Extend C, U, UM to Q4.k
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fdivsqrtfgen2 fgen2(.up, .uz, .C({2'b11, CNext}), .U({3'b000, U}), .UM({3'b000, UM}), .F);
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// Divisor multiple
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always_comb
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if (up) Dsel = DBar;
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else if (uz) Dsel = '0;
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else Dsel = D; // un
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// Partial Product Generation
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// WSA, WCA = WS + WC - qD
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mux2 #(`DIVb+4) addinmux(Dsel, F, SqrtE, AddIn);
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csa #(`DIVb+4) csa(WS, WC, AddIn, up&~SqrtE, WSA, WCA);
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assign WSNext = WSA << 1;
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assign WCNext = WCA << 1;
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// Shift thermometer code C
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assign CNext = {1'b1, C[`DIVb+1:1]};
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// Unified On-The-Fly Converter to accumulate result
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fdivsqrtuotfc2 uotfc2(.up, .un, .C(CNext), .U, .UM, .UNext, .UMNext);
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endmodule
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