mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
74 lines
1.5 KiB
Python
Executable File
74 lines
1.5 KiB
Python
Executable File
#!/usr/bin/python3
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"""
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wrapperGen.py
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kekim@hmc.edu
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script that generates top-level wrappers for verilog modules to synthesize
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"""
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import argparse
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import glob
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import os
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#create argument parser
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parser = argparse.ArgumentParser()
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parser.add_argument("DESIGN")
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parser.add_argument("HDLPATH");
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args=parser.parse_args()
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fin_path = glob.glob(f"{os.getenv('WALLY')}/src/**/{args.DESIGN}.sv",recursive=True)[0]
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fin = open(fin_path, "r", encoding='utf-8')
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lines = fin.readlines()
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# keeps track of what line number the module header begins
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lineModuleStart = 0
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# keeps track of what line number the module header ends
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lineModuleEnd = 0
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# keeps track of module name
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moduleName = ""
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# string that will keep track of the running module header
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buf = "import cvw::*;\n`include \"config.vh\"\n`include \"parameter-defs.vh\"\n"
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# are we writing into the buffer
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writeBuf=False
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index=0
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# string copy logic
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for l in lines:
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if l.lstrip().find("module") == 0:
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lineModuleStart = index
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moduleName = l.split()[1]
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writeBuf = True
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buf += f"module {moduleName}wrapper (\n"
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continue
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if (writeBuf):
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buf += l
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if l.lstrip().find (");") == 0:
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lineModuleEnd = index
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break
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index+=1
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# post-processing buffer: add DUT and endmodule lines
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buf += f"\t{moduleName} #(P) dut(.*);\nendmodule"
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# path to wrapper
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wrapperPath = f"{args.HDLPATH}/{moduleName}wrapper.sv"
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fout = open(wrapperPath, "w")
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fout.write(buf)
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fin.close()
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fout.close()
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#print(buf)
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