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https://github.com/openhwgroup/cvw
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40 lines
788 B
Systemverilog
40 lines
788 B
Systemverilog
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module sbtm2 (input logic [11:0] a, output logic [10:0] y);
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// bit partitions
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logic [4:0] x0;
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logic [2:0] x1;
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logic [3:0] x2;
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logic [2:0] x2_1cmp;
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// mem outputs
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logic [12:0] y0;
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logic [5:0] y1;
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// input to CPA
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logic [14:0] op1;
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logic [14:0] op2;
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logic [14:0] p;
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logic cout;
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assign x0 = a[11:7];
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assign x1 = a[6:4];
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assign x2 = a[3:0];
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sbtm_a2 mem1 ({x0[3:0], x1}, y0);
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assign op1 = {1'b0, y0, 1'b0};
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// 1s cmp per sbtm/stam
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assign x2_1cmp = x2[3] ? ~x2[2:0] : x2[2:0];
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sbtm_a3 mem2 ({x0, x2_1cmp}, y1);
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// 1s cmp per sbtm/stam
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assign op2 = x2[3] ? {{8{1'b1}}, ~y1, 1'b1} :
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{8'b0, y1, 1'b1};
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// CPA
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bk15 cp1 (cout, p, op1, op2, 1'b0);
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assign y = p[14:4];
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endmodule // sbtm2
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