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56 lines
1.8 KiB
Systemverilog
56 lines
1.8 KiB
Systemverilog
///////////////////////////////////////////
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// clmul.sv
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//
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// Written: Kevin Kim <kekim@hmc.edu> and Kip Macsai-Goren <kmacsaigoren@hmc.edu>
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// Created: 1 February 2023
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// Modified:
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//
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// Purpose: RISC-V single bit manipulation unit (ZBS instructions)
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//
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// Documentation: RISC-V System on Chip Design Chapter ***
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module clmul #(parameter WIDTH=32) (
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input logic [WIDTH-1:0] A, B, // Operands
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output logic [WIDTH-1:0] Result); // ZBS result
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logic [WIDTH-1:0] pp [WIDTH-1:0]; //partial AND products
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logic [WIDTH-1:0] sop; //sum of partial products
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genvar i,j;
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for (i=1; i<WIDTH;i+=WIDTH) begin:outer //loop fills partial product array
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for (j=0;j<i;j++) begin: inner
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assign pp[i][j] = A[i]&B[j];
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end
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end
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for (i=1;i<WIDTH;i++) begin:xortree
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assign result[i] = ^pp[i][i:0];
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end
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assign result[0] = A[0]&B[0];
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endmodule
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