cvw/pipelined/src/ifu
2022-12-15 09:53:35 -06:00
..
.ifu.sv.swp Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault. 2022-01-27 17:11:27 -06:00
bpred.sv Removed unused flushf. 2022-12-11 16:28:11 -06:00
BTBPredictor.sv fpu compare simplification, minor cleanup 2022-03-29 17:11:28 +00:00
CodeAligner.py Renamed wally-pipelined to pipelined 2022-01-04 19:47:41 +00:00
decompress.sv Reformatted MIT license to 95 characters 2022-01-07 12:58:40 +00:00
globalHistoryPredictor.sv Reformatted MIT license to 95 characters 2022-01-07 12:58:40 +00:00
gsharePredictor.sv replaced k with bpred size 2022-04-18 04:21:03 +00:00
ifu.sv Reworked the hazards to eliminate StallFCause. Flush and CSRWrites now flush F,D,E stages and set the correct PCNextF in the M stage. 2022-12-15 09:53:35 -06:00
irom.sv Fixed first problem with the rv64i IROM. 2022-10-11 11:35:40 -05:00
localHistoryPredictor.sv Removed unused flushf. 2022-12-11 16:28:11 -06:00
RAsPredictor.sv Reformatted MIT license to 95 characters 2022-01-07 12:58:40 +00:00
satCounter2.sv Reformatted MIT license to 95 characters 2022-01-07 12:58:40 +00:00
spillsupport.sv Removed TrapM from the LSU and IFU. TrapM is replaced with FlushW for both. (Don't like this for the IFU). 2022-11-07 15:50:55 -06:00
twoBitPredictor.sv Reformatted MIT license to 95 characters 2022-01-07 12:58:40 +00:00