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50 lines
1.6 KiB
Systemverilog
50 lines
1.6 KiB
Systemverilog
///////////////////////////////////////////
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// clockgater.sv
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//
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// Written: Ross Thompson 9 January 2021
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// Modified:
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//
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// Purpose: Clock gater model. Must use standard cell for synthesis.
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module clockgater #(parameter FPGA) (
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input logic E,
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input logic SE,
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input logic CLK,
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output logic ECLK
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);
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if (FPGA) BUFGCE bufgce_i0 (.I(CLK), .CE(E | SE), .O(ECLK));
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else begin
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// *** BUG
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// VERY IMPORTANT.
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// This part functionally models a clock gater, but does not necessarily meet the timing constrains a real standard cell would.
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// Do not use this in synthesis!
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logic enable_q;
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always_latch begin
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if(~CLK) begin
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enable_q <= E | SE;
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end
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end
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assign ECLK = enable_q & CLK;
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end
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endmodule
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