cvw/tests/debug/simple/test.ld
2024-06-09 11:46:35 -05:00

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OUTPUT_ARCH( "riscv" )
ENTRY(main)
/*----------------------------------------------------------------------*/
/* Sections */
/*----------------------------------------------------------------------*/
MEMORY {
ram(wxa!ri): ORIGIN = 0x80000000, LENGTH = 0x4000
}
SECTIONS {
.text :
{
*(.text*)
}
> ram
. = ALIGN(4);
}