mirror of
https://github.com/openhwgroup/cvw
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430 lines
20 KiB
Systemverilog
430 lines
20 KiB
Systemverilog
///////////////////////////////////////////
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// wallypipelinedcore.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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//
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// Purpose: Pipelined RISC-V Processor
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//
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// Documentation: RISC-V System on Chip Design
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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// https://github.com/openhwgroup/cvw
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
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input logic clk, reset,
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// Privileged
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input logic MTimerInt, MExtInt, SExtInt, MSwInt,
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input logic [63:0] MTIME_CLINT,
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// Bus Interface
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input logic [P.AHBW-1:0] HRDATA,
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input logic HREADY, HRESP,
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output logic HCLK, HRESETn,
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output logic [P.PA_BITS-1:0] HADDR,
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output logic [P.AHBW-1:0] HWDATA,
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output logic [P.XLEN/8-1:0] HWSTRB,
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output logic HWRITE,
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output logic [2:0] HSIZE,
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output logic [2:0] HBURST,
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output logic [3:0] HPROT,
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output logic [1:0] HTRANS,
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output logic HMASTLOCK,
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// Debug Mode Control
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input logic HaltReq,
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input logic ResumeReq,
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input logic HaltOnReset,
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input logic AckHaveReset,
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output logic ResumeAck,
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output logic HaveReset,
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output logic DebugStall,
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input logic ExecProgBuf,
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// Debug scan chain
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output logic DebugStopTime_REGW,
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input logic DebugScanEn, // puts scannable flops into scan mode
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output logic DebugScanOut, // (misc) scan chain data out
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output logic GPRScanOut, // (GPR) scan chain data out
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output logic FPRScanOut, // (FPR) scan chain data out
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output logic CSRScanOut, // (CSR) scan chain data out
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input logic DebugScanIn, // scan chain data in
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input logic MiscSel, // selects general scan chain
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input logic GPRSel, // selects GPR scan chain
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input logic FPRSel, // selects FPR scan chain
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input logic CSRSel, // selects CSR scan chain
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input logic [11:0] DebugRegAddr, // address for scanable regfiles (GPR, FPR, CSR)
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input logic DebugCapture, // latches values into scan register before scanning out
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input logic DebugRegUpdate, // writes values from scan register after scanning in
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input logic [P.XLEN-1:0] ProgBufAddr,
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input logic ProgBuffScanEn
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);
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logic StallF, StallD, StallE, StallM, StallW;
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logic FlushD, FlushE, FlushM, FlushW;
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logic TrapM, RetM;
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logic DebugMode, Step;
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logic ebreakEn;
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// signals that must connect through DP
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logic IntDivE, W64E;
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logic CSRReadM, CSRWriteM, PrivilegedM;
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logic [1:0] AtomicM;
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logic [P.XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE;
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logic [P.XLEN-1:0] SrcAM;
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logic [2:0] Funct3E;
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logic [31:0] InstrD;
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logic [31:0] InstrM, InstrOrigM;
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logic [P.XLEN-1:0] PCSpillF, PCE, PCLinkE;
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logic [P.XLEN-1:0] PCM;
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logic [P.XLEN-1:0] CSRReadValW, MDUResultW;
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logic [P.XLEN-1:0] EPCM, TrapVectorM;
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logic [1:0] MemRWE;
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logic [1:0] MemRWM;
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logic InstrValidD, InstrValidE, InstrValidM;
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logic InstrMisalignedFaultM;
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logic IllegalBaseInstrD, IllegalFPUInstrD, IllegalIEUFPUInstrD;
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logic InstrPageFaultF, LoadPageFaultM, StoreAmoPageFaultM;
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logic LoadMisalignedFaultM, LoadAccessFaultM;
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logic StoreAmoMisalignedFaultM, StoreAmoAccessFaultM;
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logic InvalidateICacheM, FlushDCacheM;
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logic PCSrcE;
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logic CSRWriteFenceM;
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logic DivBusyE;
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logic StructuralStallD;
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logic LoadStallD;
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logic StoreStallD;
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logic SquashSCW;
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logic MDUActiveE; // Mul/Div instruction being executed
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logic ENVCFG_ADUE; // HPTW A/D Update enable
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logic ENVCFG_PBMTE; // Page-based memory type enable
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logic [3:0] ENVCFG_CBE; // Cache Block operation enables
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logic [3:0] CMOpM; // 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero
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logic IFUPrefetchE, LSUPrefetchM; // instruction / data prefetch hints
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// floating point unit signals
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logic [2:0] FRM_REGW;
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logic [4:0] RdE, RdM, RdW;
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logic FPUStallD;
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logic FWriteIntE;
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logic [P.FLEN-1:0] FWriteDataM;
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logic [P.XLEN-1:0] FIntResM;
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logic [P.XLEN-1:0] FCvtIntResW;
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logic FCvtIntW;
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logic FDivBusyE;
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logic FRegWriteM;
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logic FpLoadStoreM;
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logic [4:0] SetFflagsM;
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logic [P.XLEN-1:0] FIntDivResultW;
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// memory management unit signals
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logic ITLBWriteF;
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logic ITLBMissOrUpdateAF;
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logic [P.XLEN-1:0] SATP_REGW;
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logic STATUS_MXR, STATUS_SUM, STATUS_MPRV;
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logic [1:0] STATUS_MPP, STATUS_FS;
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logic [1:0] PrivilegeModeW;
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logic [P.XLEN-1:0] PTE;
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logic [1:0] PageType;
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logic sfencevmaM;
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logic SelHPTW;
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// PMA checker signals
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/* verilator lint_off UNDRIVEN */ // these signals are undriven in configurations without a privileged unit
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var logic [P.PA_BITS-3:0] PMPADDR_ARRAY_REGW[P.PMP_ENTRIES-1:0];
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var logic [7:0] PMPCFG_ARRAY_REGW[P.PMP_ENTRIES-1:0];
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/* verilator lint_on UNDRIVEN */
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// IMem stalls
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logic IFUStallF;
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logic LSUStallM;
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// cpu lsu interface
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logic [2:0] Funct3M;
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logic [P.XLEN-1:0] IEUAdrE;
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logic [P.XLEN-1:0] WriteDataM;
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logic [P.XLEN-1:0] IEUAdrM;
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logic [P.LLEN-1:0] ReadDataW;
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logic CommittedM;
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// AHB ifu interface
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logic [P.PA_BITS-1:0] IFUHADDR;
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logic [2:0] IFUHBURST;
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logic [1:0] IFUHTRANS;
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logic [2:0] IFUHSIZE;
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logic IFUHWRITE;
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logic IFUHREADY;
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// AHB LSU interface
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logic [P.PA_BITS-1:0] LSUHADDR;
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logic [P.XLEN-1:0] LSUHWDATA;
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logic [P.XLEN/8-1:0] LSUHWSTRB;
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logic LSUHWRITE;
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logic LSUHREADY;
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logic BPWrongE, BPWrongM;
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logic BPDirWrongM;
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logic BTAWrongM;
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logic RASPredPCWrongM;
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logic IClassWrongM;
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logic [3:0] IClassM;
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logic InstrAccessFaultF, HPTWInstrAccessFaultF, HPTWInstrPageFaultF;
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logic [2:0] LSUHSIZE;
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logic [2:0] LSUHBURST;
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logic [1:0] LSUHTRANS;
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logic DCacheMiss;
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logic DCacheAccess;
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logic ICacheMiss;
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logic ICacheAccess;
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logic BigEndianM;
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logic FCvtIntE;
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logic CommittedF;
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logic BranchD, BranchE, JumpD, JumpE;
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logic DCacheStallM, ICacheStallF;
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logic wfiM, IntPendingM;
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logic ebreakM;
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// Debug mode logic
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logic [P.XLEN-1:0] DPC;
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logic DRet;
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logic DCall;
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logic [2:0] DebugCause;
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logic ForceBreakPoint;
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// Debug register scan chain interconnects
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logic [2:0] DebugScanReg;
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// instruction fetch unit: PC, branch prediction, instruction cache
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ifu #(P) ifu(.clk, .reset,
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.StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
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.InstrValidE, .InstrValidD,
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.BranchD, .BranchE, .JumpD, .JumpE, .ICacheStallF,
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// Fetch
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.HRDATA, .PCSpillF, .IFUHADDR,
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.IFUStallF, .IFUHBURST, .IFUHTRANS, .IFUHSIZE, .IFUHREADY, .IFUHWRITE,
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.ICacheAccess, .ICacheMiss,
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// Execute
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.PCLinkE, .PCSrcE, .IEUAdrE, .IEUAdrM, .PCE, .BPWrongE, .BPWrongM,
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// Mem
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.CommittedF, .EPCM, .TrapVectorM, .RetM, .TrapM, .InvalidateICacheM, .CSRWriteFenceM,
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.InstrD, .InstrM, .InstrOrigM, .PCM, .IClassM, .BPDirWrongM,
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.BTAWrongM, .RASPredPCWrongM, .IClassWrongM,
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// Faults out
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.IllegalBaseInstrD, .IllegalFPUInstrD, .InstrPageFaultF, .IllegalIEUFPUInstrD, .InstrMisalignedFaultM,
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// mmu management
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.PrivilegeModeW, .PTE, .PageType, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV,
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.STATUS_MPP, .ENVCFG_PBMTE, .ENVCFG_ADUE, .ITLBWriteF, .sfencevmaM, .ITLBMissOrUpdateAF,
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// pmp/pma (inside mmu) signals.
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.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, .InstrAccessFaultF,
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.DRet, .ProgBuffScanEn, .ProgBufAddr, .ProgBufScanIn(DebugScanIn),
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.DebugScanEn(DebugScanEn & MiscSel), .DebugScanIn(DebugScanReg[0]), .DebugScanOut(DebugScanReg[1]));
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// integer execution unit: integer register file, datapath and controller
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ieu #(P) ieu(.clk, .reset,
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// Decode Stage interface
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.InstrD, .STATUS_FS, .ENVCFG_CBE, .IllegalIEUFPUInstrD, .IllegalBaseInstrD,
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// Execute Stage interface
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.PCE, .PCLinkE, .FWriteIntE, .FCvtIntE, .IEUAdrE, .IntDivE, .W64E,
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.Funct3E, .ForwardedSrcAE, .ForwardedSrcBE, .MDUActiveE, .CMOpM, .IFUPrefetchE, .LSUPrefetchM,
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// Memory stage interface
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.SquashSCW, // from LSU
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.MemRWE, // read/write control goes to LSU
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.MemRWM, // read/write control goes to LSU
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.AtomicM, // atomic control goes to LSU
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.WriteDataM, // Write data to LSU
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.Funct3M, // size and signedness to LSU
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.SrcAM, // to privilege and fpu
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.RdE, .RdM, .FIntResM, .FlushDCacheM,
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.BranchD, .BranchE, .JumpD, .JumpE,
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// Writeback stage
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.CSRReadValW, .MDUResultW, .FIntDivResultW, .RdW, .ReadDataW(ReadDataW[P.XLEN-1:0]),
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.InstrValidM, .InstrValidE, .InstrValidD, .FCvtIntResW, .FCvtIntW,
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// hazards
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.StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
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.StructuralStallD, .LoadStallD, .StoreStallD, .PCSrcE,
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.CSRReadM, .CSRWriteM, .PrivilegedM, .CSRWriteFenceM, .InvalidateICacheM,
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.DebugScanEn, .DebugScanIn(DebugScanReg[1]), .GPRScanIn(DebugScanIn), .DebugScanOut(DebugScanReg[2]), .GPRScanOut,
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.MiscSel, .GPRSel, .DebugCapture, .DebugRegUpdate, .DebugRegAddr(DebugRegAddr[4:0]));
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lsu #(P) lsu(
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.clk, .reset, .StallM, .FlushM, .StallW, .FlushW,
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// CPU interface
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.MemRWE, .MemRWM, .Funct3M, .Funct7M(InstrM[31:25]), .AtomicM,
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.CommittedM, .DCacheMiss, .DCacheAccess, .SquashSCW,
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.FpLoadStoreM, .FWriteDataM, .IEUAdrE, .IEUAdrM, .WriteDataM,
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.ReadDataW, .FlushDCacheM, .CMOpM, .LSUPrefetchM,
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// connected to ahb (all stay the same)
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.LSUHADDR, .HRDATA, .LSUHWDATA, .LSUHWSTRB, .LSUHSIZE,
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.LSUHBURST, .LSUHTRANS, .LSUHWRITE, .LSUHREADY,
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// connect to csr or privilege and stay the same.
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.PrivilegeModeW, .BigEndianM, // connects to csr
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.PMPCFG_ARRAY_REGW, // connects to csr
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.PMPADDR_ARRAY_REGW, // connects to csr
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// hptw keep i/o
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.SATP_REGW, // from csr
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.STATUS_MXR, // from csr
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.STATUS_SUM, // from csr
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.STATUS_MPRV, // from csr
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.STATUS_MPP, // from csr
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.ENVCFG_PBMTE, // from csr
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.ENVCFG_ADUE, // from csr
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.sfencevmaM, // connects to privilege
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.DCacheStallM, // connects to privilege
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.LoadPageFaultM, // connects to privilege
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.StoreAmoPageFaultM, // connects to privilege
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.LoadMisalignedFaultM, // connects to privilege
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.LoadAccessFaultM, // connects to privilege
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.HPTWInstrAccessFaultF, // connects to privilege
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.HPTWInstrPageFaultF, // connects to privilege
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.StoreAmoMisalignedFaultM, // connects to privilege
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.StoreAmoAccessFaultM, // connects to privilege
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.PCSpillF, .ITLBMissOrUpdateAF, .PTE, .PageType, .ITLBWriteF, .SelHPTW,
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.LSUStallM, .DebugCapture, .DebugScanEn(DebugScanEn & MiscSel), .DebugScanIn(DebugScanReg[2]), .DebugScanOut);
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if(P.BUS_SUPPORTED) begin : ebu
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ebu #(P) ebu(// IFU connections
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.clk, .reset,
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// IFU interface
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.IFUHADDR, .IFUHBURST, .IFUHTRANS, .IFUHREADY, .IFUHSIZE,
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// LSU interface
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.LSUHADDR, .LSUHWDATA, .LSUHWSTRB, .LSUHSIZE, .LSUHBURST,
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.LSUHTRANS, .LSUHWRITE, .LSUHREADY,
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// BUS interface
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.HREADY, .HRESP, .HCLK, .HRESETn,
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.HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST,
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.HPROT, .HTRANS, .HMASTLOCK);
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end else begin
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assign {IFUHREADY, LSUHREADY, HCLK, HRESETn, HADDR, HWDATA,
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HWSTRB, HWRITE, HSIZE, HBURST, HPROT, HTRANS, HMASTLOCK} = '0;
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end
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// global stall and flush control
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hazard #(P) hzu(
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.BPWrongE, .CSRWriteFenceM, .RetM, .TrapM, .DRet,
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.StructuralStallD,
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.LSUStallM, .IFUStallF,
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.FPUStallD,
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.DivBusyE, .FDivBusyE,
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.wfiM, .IntPendingM, .DebugStall,
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// Stall & flush outputs
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.StallF, .StallD, .StallE, .StallM, .StallW,
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.FlushD, .FlushE, .FlushM, .FlushW);
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if (P.DEBUG_SUPPORTED) begin
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dmc debugcontrol(
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.clk, .reset,
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.Step, .ebreakM, .ebreakEn, .HaltReq, .ResumeReq, .HaltOnReset, .AckHaveReset,
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.ResumeAck, .HaveReset, .DebugMode, .DebugCause, .DebugStall, .ExecProgBuf,
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.DCall, .DRet, .ForceBreakPoint);
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end else begin
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assign {DebugMode, DebugCause, ResumeAck, HaveReset, DebugStall, DCall, DRet, ForceBreakPoint} = '0;
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end
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// privileged unit
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if (P.ZICSR_SUPPORTED) begin:priv
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privileged #(P) priv(
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.clk, .reset,
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.FlushD, .FlushE, .FlushM, .FlushW, .StallD, .StallE, .StallM, .StallW,
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.CSRReadM, .CSRWriteM, .SrcAM, .PCM,
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.InstrM, .InstrOrigM, .CSRReadValW, .EPCM, .TrapVectorM,
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.RetM, .TrapM, .sfencevmaM, .InvalidateICacheM, .DCacheStallM, .ICacheStallF,
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.InstrValidM, .CommittedM, .CommittedF,
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.FRegWriteM, .LoadStallD, .StoreStallD,
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.BPDirWrongM, .BTAWrongM, .BPWrongM,
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.RASPredPCWrongM, .IClassWrongM, .DivBusyE, .FDivBusyE,
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.IClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .PrivilegedM,
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.InstrPageFaultF, .LoadPageFaultM, .StoreAmoPageFaultM,
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.InstrMisalignedFaultM, .IllegalIEUFPUInstrD,
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.LoadMisalignedFaultM, .StoreAmoMisalignedFaultM,
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.MTimerInt, .MExtInt, .SExtInt, .MSwInt,
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.MTIME_CLINT, .IEUAdrM, .SetFflagsM,
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.InstrAccessFaultF, .HPTWInstrAccessFaultF, .HPTWInstrPageFaultF, .LoadAccessFaultM, .StoreAmoAccessFaultM, .SelHPTW,
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.PrivilegeModeW, .SATP_REGW,
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.STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .STATUS_FS,
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.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
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.FRM_REGW, .ENVCFG_CBE, .ENVCFG_PBMTE, .ENVCFG_ADUE, .wfiM, .IntPendingM, .BigEndianM, .ebreakM,
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.ebreakEn, .ForceBreakPoint, .DebugMode, .DebugCause, .Step, .DebugStopTime_REGW, .DPC, .DCall,
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.DRet, .ExecProgBuf, .DebugSel(CSRSel), .DebugRegAddr, .DebugCapture,
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.DebugRegUpdate, .DebugScanEn(DebugScanEn & CSRSel), .DebugScanIn, .DebugScanOut(CSRScanOut));
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if (P.DEBUG_SUPPORTED) begin
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flopenrs #(1) scantrapm (.clk, .reset, .en(DebugCapture), .d(TrapM), .q(),
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.scan(DebugScanEn), .scanin(DebugScanIn), .scanout(DebugScanReg[0]));
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end else begin
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assign DebugScanReg[0] = DebugScanIn;
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end
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end else begin
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assign {CSRReadValW, PrivilegeModeW,
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SATP_REGW, STATUS_MXR, STATUS_SUM, STATUS_MPRV, STATUS_MPP, STATUS_FS, FRM_REGW,
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// PMPCFG_ARRAY_REGW, PMPADDR_ARRAY_REGW,
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ENVCFG_CBE, ENVCFG_PBMTE, ENVCFG_ADUE,
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EPCM, TrapVectorM, RetM, TrapM,
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sfencevmaM, BigEndianM, wfiM, IntPendingM, CSRScanOut} = '0;
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assign DebugScanReg[0] = DebugScanIn;
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assign DebugStopTime_REGW = '0;
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end
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// multiply/divide unit
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if (P.ZMMUL_SUPPORTED) begin:mdu
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mdu #(P) mdu(.clk, .reset, .StallM, .StallW, .FlushE, .FlushM, .FlushW,
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.ForwardedSrcAE, .ForwardedSrcBE,
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.Funct3E, .Funct3M, .IntDivE, .W64E, .MDUActiveE,
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.MDUResultW, .DivBusyE);
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end else begin // no M instructions supported
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assign MDUResultW = '0;
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assign DivBusyE = 1'b0;
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end
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// floating point unit
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if (P.F_SUPPORTED) begin:fpu
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fpu #(P) fpu(
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.clk, .reset,
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.FRM_REGW, // Rounding mode from CSR
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.InstrD, // instruction from IFU
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|
.ReadDataW(ReadDataW[P.FLEN-1:0]), // Read data from memory
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.ForwardedSrcAE, // Integer input being processed (from IEU)
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|
.StallE, .StallM, .StallW, // stall signals from HZU
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|
.FlushE, .FlushM, .FlushW, // flush signals from HZU
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|
.RdE, .RdM, .RdW, // which FP register to write to (from IEU)
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.STATUS_FS, // is floating-point enabled?
|
|
.FRegWriteM, // FP register write enable
|
|
.FpLoadStoreM,
|
|
.ForwardedSrcBE, // Integer input for intdiv
|
|
.Funct3E, .Funct3M, .IntDivE, .W64E, // Integer flags and functions
|
|
.FPUStallD, // Stall the decode stage
|
|
.FWriteIntE, .FCvtIntE, // integer register write enable, conversion operation
|
|
.FWriteDataM, // Data to be written to memory
|
|
.FIntResM, // data to be written to integer register
|
|
.FCvtIntResW, // fp -> int conversion result to be stored in int register
|
|
.FCvtIntW, // fpu result selection
|
|
.FDivBusyE, // Is the divide/sqrt unit busy (stall execute stage)
|
|
.IllegalFPUInstrD, // Is the instruction an illegal fpu instruction
|
|
.SetFflagsM, // FPU flags (to privileged unit)
|
|
.FIntDivResultW,
|
|
.DebugSel(FPRSel),
|
|
.DebugRegAddr(DebugRegAddr[4:0]),
|
|
.DebugCapture,
|
|
.DebugRegUpdate,
|
|
.DebugScanEn(DebugScanEn & FPRSel),
|
|
.DebugScanIn,
|
|
.DebugScanOut(FPRScanOut));
|
|
end else begin // no F_SUPPORTED or D_SUPPORTED; tie outputs low
|
|
assign {FPUStallD, FWriteIntE, FCvtIntE, FIntResM, FCvtIntW, FRegWriteM,
|
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IllegalFPUInstrD, SetFflagsM, FpLoadStoreM,
|
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FWriteDataM, FCvtIntResW, FIntDivResultW, FDivBusyE, FPRScanOut} = '0;
|
|
end
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endmodule
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