David Harris 325724f556 LSU Cleanup		2022-01-15 01:11:17 +00:00
..
slack-notifier
wave-dos	Moved Dcache into bus block	2022-01-15 00:39:07 +00:00
buildrootBugFinder.py
fpga-wave.do	Moved Dcache into bus block	2022-01-15 00:39:07 +00:00
lint-wally
linux-wave.do	Moved Dcache into bus block	2022-01-15 00:39:07 +00:00
make-tests.sh
Makefile	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-01-06 23:04:33 +00:00
regression-wally	LSU Cleanup	2022-01-15 01:11:17 +00:00
sim-buildroot
sim-buildroot-batch
sim-coremark-batch
sim-fp64
sim-fp64-batch
sim-wally	LSU Cleanup	2022-01-15 01:11:17 +00:00
sim-wally-batch	Renamed LSUStall to LSUStallM	2022-01-15 00:24:16 +00:00
wally-buildroot-batch.do
wally-buildroot.do
wally-coremark.do	Improve wavefile by adding performance counters.	2022-01-12 10:53:29 -06:00
wally-fp64-batch.do
wally-fp64.do
wally-harvard.do	Added support for logic memory in the IFU and LSU. This disables the bus interface. Peripherals do not work. Also requires using testbench-harvard.sv. I hope to merge this testbench with the main testbench.sv soon.	2022-01-13 22:21:43 -06:00
wally-pipelined-batch.do
wally-pipelined-fpga.do
wally-pipelined-tim-batch.do	Added tim only test to regression-wally. Minor cleanup to ifu.	2022-01-14 11:13:06 -06:00
wally-pipelined-tim.do	Added tim only test to regression-wally. Minor cleanup to ifu.	2022-01-14 11:13:06 -06:00
wally-pipelined.do
wave-all.do
wave-coremark.do	Moved Dcache into bus block	2022-01-15 00:39:07 +00:00
wave.do	Moved Dcache into bus block	2022-01-15 00:39:07 +00:00