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39 lines
1.4 KiB
Systemverilog
39 lines
1.4 KiB
Systemverilog
///////////////////////////////////////////
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//
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// Written: me@KatherineParry.com
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// Modified: 7/5/2022
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//
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// Purpose: Leading Zero Counter
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module lzc #(parameter WIDTH = 1) (
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input logic [WIDTH-1:0] num, // number to count the leading zeroes of
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output logic [$clog2(WIDTH+1)-1:0] ZeroCnt // the number of leading zeroes
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);
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integer i;
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always_comb begin
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i = 0;
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while (~num[WIDTH-1-i] & (i < WIDTH)) i = i+1; // search for leading one
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ZeroCnt = i[$clog2(WIDTH)-1:0];
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end
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endmodule
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