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41 lines
1.5 KiB
Systemverilog
41 lines
1.5 KiB
Systemverilog
///////////////////////////////////////////
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// csa.sv
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//
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// Written: Katherine Parry and David_Harris@hmc.edu 21 August 2022
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// Modified:
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//
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// Purpose: 3:2 carry-save adder
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module csa #(parameter N=16) (
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input logic [N-1:0] x, y, z,
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input logic cin,
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output logic [N-1:0] s, c
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);
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// This block adds x, y, z, and cin to produce
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// a result s / c in carry-save redundant form.
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// cin is just added to the least significant bit
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// s + c = x + y + z + cin
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assign s = x ^ y ^ z;
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assign c = {x[N-2:0] & (y[N-2:0] | z[N-2:0]) | (y[N-2:0] & z[N-2:0]), cin};
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endmodule
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