mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
152 lines
6.2 KiB
Plaintext
152 lines
6.2 KiB
Plaintext
# wally.do
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# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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#
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# Modification by Oklahoma State University & Harvey Mudd College
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# Use with Testbench
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# James Stine, 2008; David Harris 2021
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# Go Cowboys!!!!!!
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#
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# Takes 1:10 to run RV64IC tests using gui
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# run with vsim -do "do wally-pipelined.do rv64ic riscvarchtest-64m"
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# Use this wally-pipelined.do file to run this example.
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# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
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# do wally.do
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# or, to run from a shell, type the following at the shell prompt:
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# vsim -do wally.do -c
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# (omit the "-c" to see the GUI while running from the shell)
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onbreak {resume}
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# create library
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if [file exists work] {
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vdel -all
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}
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vlib work
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# compile source files
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# suppress spurious warnngs about
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# "Extra checking for conflicts with always_comb done at vopt time"
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# because vsim will run vopt
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# start and run simulation
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# remove +acc flag for faster sim during regressions if there is no need to access internal signals
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if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
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vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
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# start and run simulation
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vopt work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -G NO_SPOOFING=0 -o testbenchopt
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vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829,13286 -fatal 7
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#-- Run the Simulation
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#run -all
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add log -recursive /*
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do linux-wave.do
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run -all
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exec ./slack-notifier/slack-notifier.py
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} elseif {$2 eq "buildroot-no-trace"} {
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vlog -lint -work work_${1}_${2} \
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+define+USE_IMPERAS_DV \
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+incdir+../config/$1 \
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+incdir+../config/shared \
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+incdir+$env(IMPERAS_HOME)/ImpPublic/include/host \
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+incdir+$env(IMPERAS_HOME)/ImpProprietary/include/host \
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$env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvviApiPkg.sv \
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$env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvviTrace.sv \
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$env(IMPERAS_HOME)/ImpProprietary/source/host/idv/idvPkg.sv \
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$env(IMPERAS_HOME)/ImpProprietary/source/host/idv/idvApiPkg.sv \
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$env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2api.sv \
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$env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2log.sv \
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$env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2cov.sv \
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../src/cvw.sv \
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../testbench/testbench-linux-imperas.sv \
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../testbench/common/*.sv ../src/*/*.sv \
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../src/*/*/*.sv -suppress 2583
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#
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# start and run simulation
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# for profiling add
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# vopt -fprofile
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# vsim -fprofile+perf
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# visualizer -fprofile+perf+dir=fprofile
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#
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eval vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 \
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-G INSTR_LIMIT=0 -G INSTR_WAVEON=0 -G CHECKPOINT=0 -G NO_SPOOFING=1 -o testbenchopt
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eval vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829,13286 -fatal 7 \
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-sv_lib $env(IMPERAS_HOME)/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model \
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$env(OTHERFLAGS)
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#-- Run the Simulation
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echo "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!"
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echo "Don't forget to change DEBUG_LEVEL = 0."
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echo "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!"
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#run 100 ns
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#force -deposit testbench/dut/core/priv/priv/csr/csri/IE_REGW 16'h2aa
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#force -deposit testbench/dut/uncore/uncore/clint/clint/MTIMECMP 64'h1000
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run 14000 ms
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#add log -recursive /*
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#do linux-wave.do
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#run -all
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exec ./slack-notifier/slack-notifier.py
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} elseif {$2 eq "fpga"} {
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echo "hello"
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vlog -work work +incdir+../config/fpga +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/sdc/*.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv ../../fpga/sim/*.sv -suppress 8852,12070,3084,3829,2583,7063,13286
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vopt +acc work.testbench -G TEST=$2 -G DEBUG=0 -o workopt
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vsim workopt +nowarn3829 -fatal 7
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do fpga-wave.do
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add log -r /*
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run 20 ms
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} else {
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if {$2 eq "ahb"} {
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vlog +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583,13286 -suppress 7063 +define+RAM_LATENCY=$3 +define+BURST_EN=$4
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} else {
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# *** modelsim won't take `PA_BITS, but will take other defines for the lengths of DTIM_RANGE and IROM_LEN. For now just live with the warnings.
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vlog +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583,13286 -suppress 7063
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}
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vopt +acc work.testbench -G TEST=$2 -G DEBUG=1 -o workopt
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vsim workopt +nowarn3829 -fatal 7
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view wave
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#-- display input and output signals as hexidecimal values
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#do ./wave-dos/peripheral-waves.do
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add log -recursive /*
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do wave.do
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#do wave-bus.do
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# power add generates the logging necessary for saif generation.
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#power add -r /dut/core/*
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#-- Run the Simulation
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run -all
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#power off -r /dut/core/*
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#power report -all -bsaif power.saif
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noview ../testbench/testbench.sv
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view wave
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}
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#elseif {$2 eq "buildroot-no-trace""} {
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# vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
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# start and run simulation
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# vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=470350800 -G INSTR_WAVEON=470350800 -G CHECKPOINT=470350800 -G DEBUG_TRACE=0 -o testbenchopt
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# vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829
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#-- Run the Simulation
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# run 100 ns
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# force -deposit testbench/dut/core/priv/priv/csr/csri/IE_REGW 16'h2aa
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# force -deposit testbench/dut/uncore/uncore/clint/clint/MTIMECMP 64'h1000
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# add log -recursive /*
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# do linux-wave.do
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# run -all
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# exec ./slack-notifier/slack-notifier.py
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#}
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