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270 lines
12 KiB
Systemverilog
270 lines
12 KiB
Systemverilog
///////////////////////////////////////////
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//
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// Written: me@KatherineParry.com
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// Modified: 7/5/2022
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//
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// Purpose: unpack input
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module unpackinput (
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input logic [`FLEN-1:0] In, // inputs from register file
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input logic En, // enable the input
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input logic [`FMTBITS-1:0] Fmt, // format signal 00 - single 01 - double 11 - quad 10 - half
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output logic Sgn, // sign bits of XYZ
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output logic [`NE-1:0] Exp, // exponents of XYZ (converted to largest supported precision)
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output logic [`NF:0] Man, // mantissas of XYZ (converted to largest supported precision)
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output logic NaN, // is XYZ a NaN
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output logic SNaN, // is XYZ a signaling NaN
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output logic Zero, // is XYZ zero
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output logic Inf, // is XYZ infinity
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output logic ExpNonZero, // is the exponent not zero
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output logic FracZero, // is the fraction zero
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output logic ExpMax // does In have the maximum exponent (NaN or Inf)
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);
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logic [`NF-1:0] Frac; //Fraction of XYZ
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logic ExpZero;
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logic BadNaNBox;
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if (`FPSIZES == 1) begin // if there is only one floating point format supported
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assign BadNaNBox = 0;
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assign Sgn = In[`FLEN-1]; // sign bit
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assign Frac = In[`NF-1:0]; // fraction (no assumed 1)
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assign ExpNonZero = |In[`FLEN-2:`NF]; // is the exponent non-zero
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assign Exp = {In[`FLEN-2:`NF+1], In[`NF]|~ExpNonZero}; // exponent. Denormalized numbers have effective biased exponent of 1
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assign ExpMax = &In[`FLEN-2:`NF]; // is the exponent all 1's
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end else if (`FPSIZES == 2) begin // if there are 2 floating point formats supported
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//***need better names for these constants
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// largest format | smaller format
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//----------------------------------
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// `FLEN | `LEN1 length of floating point number
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// `NE | `NE1 length of exponent
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// `NF | `NF1 length of fraction
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// `BIAS | `BIAS1 exponent's bias value
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// `FMT | `FMT1 precision's format value - Q=11 D=01 S=00 H=10
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// Possible combinantions specified by spec:
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// double and single
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// single and half
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// Not needed but can also handle:
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// quad and double
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// quad and single
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// quad and half
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// double and half
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assign BadNaNBox = ~(Fmt|(&In[`FLEN-1:`LEN1])); // Check NaN boxing
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// choose sign bit depending on format - 1=larger precsion 0=smaller precision
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assign Sgn = Fmt ? In[`FLEN-1] : In[`LEN1-1];
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// extract the fraction, add trailing zeroes to the mantissa if nessisary
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assign Frac = Fmt ? In[`NF-1:0] : {In[`NF1-1:0], (`NF-`NF1)'(0)};
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// is the exponent non-zero
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assign ExpNonZero = Fmt ? |In[`FLEN-2:`NF] : |In[`LEN1-2:`NF1];
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// example double to single conversion:
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// 1023 = 0011 1111 1111
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// 127 = 0000 0111 1111 (subtract this)
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// 896 = 0011 1000 0000
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// sexp = 0000 bbbb bbbb (add this) b = bit d = ~b
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// dexp = 0bdd dbbb bbbb
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// also need to take into account possible zero/denorm/inf/NaN values
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// extract the exponent, converting the smaller exponent into the larger precision if nessisary
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// - if the original precision had a denormal number convert the exponent value 1
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assign Exp = Fmt ? {In[`FLEN-2:`NF+1], In[`NF]|~ExpNonZero} : {In[`LEN1-2], {`NE-`NE1{~In[`LEN1-2]}}, In[`LEN1-3:`NF1+1], In[`NF1]|~ExpNonZero};
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// is the exponent all 1's
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assign ExpMax = Fmt ? &In[`FLEN-2:`NF] : &In[`LEN1-2:`NF1];
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end else if (`FPSIZES == 3) begin // three floating point precsions supported
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//***need better names for these constants
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// largest format | larger format | smallest format
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//---------------------------------------------------
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// `FLEN | `LEN1 | `LEN2 length of floating point number
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// `NE | `NE1 | `NE2 length of exponent
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// `NF | `NF1 | `NF2 length of fraction
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// `BIAS | `BIAS1 | `BIAS2 exponent's bias value
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// `FMT | `FMT1 | `FMT2 precision's format value - Q=11 D=01 S=00 H=10
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// Possible combinantions specified by spec:
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// quad and double and single
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// double and single and half
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// Not needed but can also handle:
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// quad and double and half
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// quad and single and half
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// Check NaN boxing
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always_comb
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case (Fmt)
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`FMT: BadNaNBox = 0;
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`FMT1: BadNaNBox = ~&In[`FLEN-1:`LEN1];
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`FMT2: BadNaNBox = ~&In[`FLEN-1:`LEN2];
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default: BadNaNBox = 1'bx;
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endcase
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// extract the sign bit
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always_comb
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case (Fmt)
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`FMT: Sgn = In[`FLEN-1];
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`FMT1: Sgn = In[`LEN1-1];
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`FMT2: Sgn = In[`LEN2-1];
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default: Sgn = 1'bx;
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endcase
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// extract the fraction
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always_comb
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case (Fmt)
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`FMT: Frac = In[`NF-1:0];
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`FMT1: Frac = {In[`NF1-1:0], (`NF-`NF1)'(0)};
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`FMT2: Frac = {In[`NF2-1:0], (`NF-`NF2)'(0)};
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default: Frac = {`NF{1'bx}};
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endcase
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// is the exponent non-zero
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always_comb
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case (Fmt)
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`FMT: ExpNonZero = |In[`FLEN-2:`NF]; // if input is largest precision (`FLEN - ie quad or double)
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`FMT1: ExpNonZero = |In[`LEN1-2:`NF1]; // if input is larger precsion (`LEN1 - double or single)
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`FMT2: ExpNonZero = |In[`LEN2-2:`NF2]; // if input is smallest precsion (`LEN2 - single or half)
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default: ExpNonZero = 1'bx;
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endcase
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// example double to single conversion:
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// 1023 = 0011 1111 1111
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// 127 = 0000 0111 1111 (subtract this)
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// 896 = 0011 1000 0000
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// sexp = 0000 bbbb bbbb (add this) b = bit d = ~b
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// dexp = 0bdd dbbb bbbb
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// also need to take into account possible zero/denorm/inf/NaN values
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// convert the larger precision's exponent to use the largest precision's bias
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always_comb
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case (Fmt)
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`FMT: Exp = {In[`FLEN-2:`NF+1], In[`NF]|~ExpNonZero};
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`FMT1: Exp = {In[`LEN1-2], {`NE-`NE1{~In[`LEN1-2]}}, In[`LEN1-3:`NF1+1], In[`NF1]|~ExpNonZero};
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`FMT2: Exp = {In[`LEN2-2], {`NE-`NE2{~In[`LEN2-2]}}, In[`LEN2-3:`NF2+1], In[`NF2]|~ExpNonZero};
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default: Exp = {`NE{1'bx}};
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endcase
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// is the exponent all 1's
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always_comb
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case (Fmt)
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`FMT: ExpMax = &In[`FLEN-2:`NF];
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`FMT1: ExpMax = &In[`LEN1-2:`NF1];
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`FMT2: ExpMax = &In[`LEN2-2:`NF2];
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default: ExpMax = 1'bx;
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endcase
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end else if (`FPSIZES == 4) begin // if all precsisons are supported - quad, double, single, and half
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// quad | double | single | half
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//-------------------------------------------------------------------
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// `Q_LEN | `D_LEN | `S_LEN | `H_LEN length of floating point number
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// `Q_NE | `D_NE | `S_NE | `H_NE length of exponent
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// `Q_NF | `D_NF | `S_NF | `H_NF length of fraction
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// `Q_BIAS | `D_BIAS | `S_BIAS | `H_BIAS exponent's bias value
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// `Q_FMT | `D_FMT | `S_FMT | `H_FMT precision's format value - Q=11 D=01 S=00 H=10
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// Check NaN boxing
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always_comb
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case (Fmt)
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2'b11: BadNaNBox = 0;
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2'b01: BadNaNBox = ~&In[`Q_LEN-1:`D_LEN];
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2'b00: BadNaNBox = ~&In[`Q_LEN-1:`S_LEN];
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2'b10: BadNaNBox = ~&In[`Q_LEN-1:`H_LEN];
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endcase
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// extract sign bit
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always_comb
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case (Fmt)
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2'b11: Sgn = In[`Q_LEN-1];
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2'b01: Sgn = In[`D_LEN-1];
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2'b00: Sgn = In[`S_LEN-1];
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2'b10: Sgn = In[`H_LEN-1];
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endcase
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// extract the fraction
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always_comb
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case (Fmt)
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2'b11: Frac = In[`Q_NF-1:0];
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2'b01: Frac = {In[`D_NF-1:0], (`Q_NF-`D_NF)'(0)};
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2'b00: Frac = {In[`S_NF-1:0], (`Q_NF-`S_NF)'(0)};
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2'b10: Frac = {In[`H_NF-1:0], (`Q_NF-`H_NF)'(0)};
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endcase
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// is the exponent non-zero
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always_comb
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case (Fmt)
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2'b11: ExpNonZero = |In[`Q_LEN-2:`Q_NF];
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2'b01: ExpNonZero = |In[`D_LEN-2:`D_NF];
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2'b00: ExpNonZero = |In[`S_LEN-2:`S_NF];
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2'b10: ExpNonZero = |In[`H_LEN-2:`H_NF];
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endcase
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// example double to single conversion:
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// 1023 = 0011 1111 1111
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// 127 = 0000 0111 1111 (subtract this)
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// 896 = 0011 1000 0000
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// sexp = 0000 bbbb bbbb (add this) b = bit d = ~b
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// dexp = 0bdd dbbb bbbb
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// also need to take into account possible zero/denorm/inf/NaN values
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// convert the double precsion exponent into quad precsion
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always_comb
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case (Fmt)
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2'b11: Exp = {In[`Q_LEN-2:`Q_NF+1], In[`Q_NF]|~ExpNonZero};
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2'b01: Exp = {In[`D_LEN-2], {`Q_NE-`D_NE{~In[`D_LEN-2]}}, In[`D_LEN-3:`D_NF+1], In[`D_NF]|~ExpNonZero};
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2'b00: Exp = {In[`S_LEN-2], {`Q_NE-`S_NE{~In[`S_LEN-2]}}, In[`S_LEN-3:`S_NF+1], In[`S_NF]|~ExpNonZero};
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2'b10: Exp = {In[`H_LEN-2], {`Q_NE-`H_NE{~In[`H_LEN-2]}}, In[`H_LEN-3:`H_NF+1], In[`H_NF]|~ExpNonZero};
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endcase
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// is the exponent all 1's
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always_comb
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case (Fmt)
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2'b11: ExpMax = &In[`Q_LEN-2:`Q_NF];
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2'b01: ExpMax = &In[`D_LEN-2:`D_NF];
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2'b00: ExpMax = &In[`S_LEN-2:`S_NF];
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2'b10: ExpMax = &In[`H_LEN-2:`H_NF];
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endcase
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end
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// Output logic
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assign FracZero = ~|Frac; // is the fraction zero?
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assign Man = {ExpNonZero, Frac}; // add the assumed one (or zero if denormal or zero) to create the significand
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assign NaN = ((ExpMax & ~FracZero)|BadNaNBox)&En; // is the input a NaN?
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assign SNaN = NaN&~Frac[`NF-1]&~BadNaNBox; // is the input a singnaling NaN?
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assign Inf = ExpMax & FracZero &En; // is the input infinity?
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assign Zero = ~ExpNonZero & FracZero; // is the input zero?
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endmodule |