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https://github.com/openhwgroup/cvw
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102 lines
3.3 KiB
Makefile
102 lines
3.3 KiB
Makefile
dst := IP
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all: ArtyA7
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.PHONY: ArtyA7 vcu118 vcu108
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ArtyA7: export XILINX_PART := xc7a100tcsg324-1
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ArtyA7: export XILINX_BOARD := digilentinc.com:arty-a7-100:part0:1.1
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ArtyA7: export board := ArtyA7
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ArtyA7: export SYSTEMCLOCK := 20000000
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ArtyA7: export MAXSDCCLOCK := 5000000
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ArtyA7: FPGA_Arty
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vcu118: export XILINX_PART := xcvu9p-flga2104-2L-e
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vcu118: export XILINX_BOARD := xilinx.com:vcu118:part0:2.4
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vcu118: export board := vcu118
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vcu118: export SYSTEMCLOCK := 71000000
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vcu118: export MAXSDCCLOCK := 1000000
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vcu118: FPGA_VCU
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vcu108: export XILINX_PART := xcvu095-ffva2104-2-e
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vcu108: export XILINX_BOARD := xilinx.com:vcu108:part0:1.7
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vcu108: export board := vcu108
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vcu108: export SYSTEMCLOCK := 50000000
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vcu108: export MAXSDCCLOCK := 12500000
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vcu108: FPGA_VCU
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# variables computed from config
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EXT_MEM_BASE = $(shell grep 'EXT_MEM_BASE' ../../config/deriv/fpga$(board)/config.vh | sed 's/.*=.*h\([[:alnum:]]*\);/0x\1/g')
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EXT_MEM_RANGE = $(shell grep 'EXT_MEM_RANGE' ../../config/deriv/fpga$(board)/config.vh | sed 's/.*=.*h\([[:alnum:]]*\);/\1/g' | sed 's/\(.*\)/base=16;\1+1/g' | bc | sed 's/\(.*\)/0x\1/g')
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.PHONY: FPGA_Arty FPGA_VCU
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FPGA_Arty: PreProcessFiles IP_Arty zsbl
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vivado -mode tcl -source wally.tcl 2>&1 | tee wally.log
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FPGA_VCU: PreProcessFiles IP_VCU zsbl
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vivado -mode tcl -source wally.tcl 2>&1 | tee wally.log
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# Generate IP Blocks
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.PHONY: IP_Arty IP_VCU
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IP_VCU: $(dst)/sysrst.log \
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MEM_VCU \
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$(dst)/clkconverter.log \
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$(dst)/ahbaxibridge.log
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IP_Arty: $(dst)/sysrst.log \
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MEM_Arty \
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$(dst)/mmcm.log \
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$(dst)/clkconverter.log \
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$(dst)/ahbaxibridge.log
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# Generate Memory IP Blocks
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.PHONY: MEM_VCU MEM_Arty
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MEM_VCU:
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$(MAKE) $(dst)/ddr4-$(board).log
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MEM_Arty:
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$(MAKE) $(dst)/ddr3-$(board).log
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# Copy files and make necessary modifications
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.PHONY: PreProcessFiles
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PreProcessFiles:
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$(MAKE) -C ../../sim deriv
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rm -rf ../src/CopiedFiles_do_not_add_to_repo/
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cp -r ../../src/ ../src/CopiedFiles_do_not_add_to_repo/
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cp -r ../../addins/verilog-ethernet/*/*.sv ../src/CopiedFiles_do_not_add_to_repo/rvvi
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cp -r ../../addins/verilog-ethernet/*/*/*/*.sv ../src/CopiedFiles_do_not_add_to_repo/rvvi
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mkdir ../src/CopiedFiles_do_not_add_to_repo/config/
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cp ../../config/deriv/fpga$(board)/config.vh ../src/CopiedFiles_do_not_add_to_repo/config/
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./insert_debug_comment.sh
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# This line allows the Bootloader to be loaded in a Block RAM on the FPGA
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sed -i "s/bit \[DATA_WIDTH-1:0\].*ROM.*/(\* rom_style=\"block\" \*) &/g" ../src/CopiedFiles_do_not_add_to_repo/generic/mem/rom1p1r.sv
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sed -i 's/$$WALLY/\.\.\/\.\.\/\.\.\//g' ../src/CopiedFiles_do_not_add_to_repo/generic/mem/rom1p1r.sv
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sed -i 's/$$WALLY/\.\.\/\.\.\/\.\.\//g' ../src/CopiedFiles_do_not_add_to_repo/generic/mem/ram1p1rwbe.sv
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# build the Zero stage boot loader (ZSBL)
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.PHONY: zsbl
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zsbl:
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$(MAKE) -C ../zsbl clean
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SYSTEMCLOCK=$(SYSTEMCLOCK) EXT_MEM_BASE=$(EXT_MEM_BASE) EXT_MEM_RANGE=$(EXT_MEM_RANGE) $(MAKE) -C ../zsbl
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# Generate Individual IP Blocks
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$(dst)/%.log: %.tcl
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mkdir -p IP
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cd IP;\
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vivado -mode batch -source ../$*.tcl | tee $*.log
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# Clean
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.PHONY: cleanIP cleanLogs cleanFPGA cleanAll
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cleanIP:
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rm -rf IP
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cleanLogs:
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rm -rf *.jou *.log
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cleanFPGA:
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rm -rf WallyFPGA.* reports sim .Xil
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cleanAll: cleanIP cleanLogs cleanFPGA
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# Aliases
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.PHONY: arty artya7 VCU118 VCU108
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arty artya7: ArtyA7
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VCU118: vcu118
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VCU108: vcu108
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