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Configurable RISC-V Processor
414 Commits 5 Branches 2 Tags 53 MiB
SystemVerilog 33.7%
Python 19.2%
Assembly 17.5%
Tcl 16.2%
C 5.8%
Other 7.4%
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Teo Ene a3aa103dc7 Fix typo from last commit
2021-03-24 17:09:58 -05:00
sky130
wally-pipelined Fix typo from last commit 2021-03-24 17:09:58 -05:00
.gitignore Added debug option to disable the function radix if not needed. 2021-03-10 15:17:02 -06:00
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riscv-wally

Configurable RISC-V Processor