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80 lines
4.1 KiB
Systemverilog
80 lines
4.1 KiB
Systemverilog
///////////////////////////////////////////
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// pmpchecker.sv
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//
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// Written: tfleming@hmc.edu & jtorrey@hmc.edu 28 April 2021
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// Modified:
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//
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// Purpose: Examines all physical memory accesses and checks them against the
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// current values of the physical memory protection (PMP) registers.
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// Can raise an access fault on illegal reads, writes, and instruction
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// fetches.
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//
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// Documentation: RISC-V System on Chip Design Chapter 8
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module pmpchecker (
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input logic [`PA_BITS-1:0] PhysicalAddress,
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input logic [1:0] PrivilegeModeW,
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// ModelSim has a switch -svinputport which controls whether input ports
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// are nets (wires) or vars by default. The default setting of this switch is
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// `relaxed`, which means that signals are nets if and only if they are
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// scalars or one-dimensional vectors. Since this is a two-dimensional vector,
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// this will be understood as a var. However, if we don't supply the `var`
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// keyword, the compiler warns us that it's interpreting the signal as a var,
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// which we might not intend.
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input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],
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input var logic [`PA_BITS-3:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0],
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input logic ExecuteAccessF, WriteAccessM, ReadAccessM,
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output logic PMPInstrAccessFaultF,
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output logic PMPLoadAccessFaultM,
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output logic PMPStoreAmoAccessFaultM
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);
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// Bit i is high when the address falls in PMP region i
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logic EnforcePMP; // should PMP be checked in this privilege level
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logic [`PMP_ENTRIES-1:0] Match; // physical address matches one of the pmp ranges
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logic [`PMP_ENTRIES-1:0] FirstMatch; // onehot encoding for the first pmpaddr to match the current address.
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logic [`PMP_ENTRIES-1:0] Active; // PMP register i is non-null
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logic [`PMP_ENTRIES-1:0] L, X, W, R; // PMP matches and has flag set
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logic [`PMP_ENTRIES-1:0] PAgePMPAdr; // for TOR PMP matching, PhysicalAddress > PMPAdr[i]
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if (`PMP_ENTRIES > 0) // prevent complaints about array of no elements when PMP_ENTRIES = 0
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pmpadrdec pmpadrdecs[`PMP_ENTRIES-1:0](
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.PhysicalAddress,
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.PMPCfg(PMPCFG_ARRAY_REGW),
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.PMPAdr(PMPADDR_ARRAY_REGW),
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.PAgePMPAdrIn({PAgePMPAdr[`PMP_ENTRIES-2:0], 1'b1}),
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.PAgePMPAdrOut(PAgePMPAdr),
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.Match, .Active, .L, .X, .W, .R);
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priorityonehot #(`PMP_ENTRIES) pmppriority(.a(Match), .y(FirstMatch)); // combine the match signal from all the adress decoders to find the first one that matches.
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// Only enforce PMP checking for S and U modes or in Machine mode when L bit is set in selected region
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assign EnforcePMP = (PrivilegeModeW == `M_MODE) ? |(L & FirstMatch) : |Active;
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// assign EnforcePMP = (PrivilegeModeW != `M_MODE) | |(L & FirstMatch); // *** switch to this logic when PMP is initialized for non-machine mode
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// *** remove unused Active lines from pmpadrdecs
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assign PMPInstrAccessFaultF = EnforcePMP & ExecuteAccessF & ~|(X & FirstMatch) ;
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assign PMPStoreAmoAccessFaultM = EnforcePMP & WriteAccessM & ~|(W & FirstMatch) ;
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assign PMPLoadAccessFaultM = EnforcePMP & ReadAccessM & ~|(R & FirstMatch) ;
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endmodule
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