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76 lines
2.7 KiB
Systemverilog
76 lines
2.7 KiB
Systemverilog
///////////////////////////////////////////
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// fdivsqrtcycles.sv
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//
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// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu, amaiuolo@hmc.edu
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// Modified: 18 April 2022
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//
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// Purpose: Determine number of cycles for divsqrt
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//
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// Documentation: RISC-V System on Chip Design Chapter 13
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module fdivsqrtcycles import cvw::*; #(parameter cvw_t P) (
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input logic [P.FMTBITS-1:0] FmtE,
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input logic SqrtE,
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input logic IntDivE,
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input logic [P.DIVBLEN:0] nE,
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output logic [P.DURLEN-1:0] CyclesE
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);
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logic [P.DURLEN+1:0] Nf, fbits; // number of fractional bits
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// DIVN = P.NF+3
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// NS = NF + 1
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// N = NS or NS+2 for div/sqrt.
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/* verilator lint_off WIDTH */
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if (P.FPSIZES == 1)
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assign Nf = P.NF;
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else if (P.FPSIZES == 2)
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always_comb
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case (FmtE)
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1'b0: Nf = P.NF1;
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1'b1: Nf = P.NF;
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endcase
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else if (P.FPSIZES == 3)
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always_comb
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case (FmtE)
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P.FMT: Nf = P.NF;
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P.FMT1: Nf = P.NF1;
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P.FMT2: Nf = P.NF2;
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default: Nf = 'x; // shouldn't happen
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endcase
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else if (P.FPSIZES == 4)
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always_comb
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case(FmtE)
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P.S_FMT: Nf = P.S_NF;
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P.D_FMT: Nf = P.D_NF;
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P.H_FMT: Nf = P.H_NF;
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P.Q_FMT: Nf = P.Q_NF;
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endcase
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always_comb begin
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if (SqrtE) fbits = Nf + 2 + 2; // Nf + two fractional bits for round/guard + 2 for right shift by up to 2
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else fbits = Nf + 2 + P.LOGR; // Nf + two fractional bits for round/guard + integer bits - try this when placing results in msbs
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if (P.IDIV_ON_FPU) CyclesE = IntDivE ? ((nE + 1)/P.DIVCOPIES) : (fbits + (P.LOGR*P.DIVCOPIES)-1)/(P.LOGR*P.DIVCOPIES);
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else CyclesE = (fbits + (P.LOGR*P.DIVCOPIES)-1)/(P.LOGR*P.DIVCOPIES);
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end
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/* verilator lint_on WIDTH */
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endmodule
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