mirror of
https://github.com/openhwgroup/cvw
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252 lines
10 KiB
Systemverilog
252 lines
10 KiB
Systemverilog
`include "wally-config.vh"
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`define NUM_REGS 32
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`define NUM_CSRS 4096
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`define PRINT_PC_INSTR 1
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`define PRINT_MOST 1
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`define PRINT_ALL 0
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module rvviTrace #(
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parameter int ILEN = `XLEN, // Instruction length in bits
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parameter int XLEN = `XLEN, // GPR length in bits
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parameter int FLEN = `FLEN, // FPR length in bits
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parameter int VLEN = 0, // Vector register size in bits
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parameter int NHART = 1, // Number of harts reported
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parameter int RETIRE = 1) // Number of instructions that can retire during valid event
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();
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localparam NUMREGS = `E_SUPPORTED ? 16 : 32;
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// wally specific signals
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logic reset;
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logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, PCW;
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logic [`XLEN-1:0] InstrRawD, InstrRawE, InstrRawM, InstrRawW;
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logic InstrValidM, InstrValidW;
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logic StallE, StallM, StallW;
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logic FlushD, FlushE, FlushM, FlushW;
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logic TrapM, TrapW;
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logic IntrF, IntrD, IntrE, IntrM, IntrW;
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logic HaltM, HaltW;
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logic [1:0] PrivilegeModeW;
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logic [`XLEN-1:0] rf[NUMREGS];
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logic [NUMREGS-1:0] rf_wb;
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logic [4:0] rf_a3;
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logic rf_we3;
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logic [`XLEN-1:0] frf[32];
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logic [`NUM_REGS-1:0] frf_wb;
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logic [4:0] frf_a4;
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logic frf_we4;
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logic [`XLEN-1:0] CSRArray [logic[11:0]];
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logic CSRWriteM, CSRWriteW;
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logic [11:0] CSRAdrM, CSRAdrW;
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// tracer signals
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logic clk;
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logic valid;
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logic [63:0] order [(NHART-1):0][(RETIRE-1):0];
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logic [ILEN-1:0] insn [(NHART-1):0][(RETIRE-1):0];
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logic intr [(NHART-1):0][(RETIRE-1):0];
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logic [(XLEN-1):0] pc_rdata [(NHART-1):0][(RETIRE-1):0];
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logic [(XLEN-1):0] pc_wdata [(NHART-1):0][(RETIRE-1):0];
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logic trap [(NHART-1):0][(RETIRE-1):0];
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logic halt [(NHART-1):0][(RETIRE-1):0];
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logic [1:0] mode [(NHART-1):0][(RETIRE-1):0];
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logic [1:0] ixl [(NHART-1):0][(RETIRE-1):0];
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logic [`NUM_REGS-1:0][(XLEN-1):0] x_wdata [(NHART-1):0][(RETIRE-1):0];
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logic [`NUM_REGS-1:0] x_wb [(NHART-1):0][(RETIRE-1):0];
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logic [`NUM_REGS-1:0][(XLEN-1):0] f_wdata [(NHART-1):0][(RETIRE-1):0];
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logic [`NUM_REGS-1:0] f_wb [(NHART-1):0][(RETIRE-1):0];
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logic [4095:0][(XLEN-1):0] csr [(NHART-1):0][(RETIRE-1):0];
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logic [4095:0] csr_wb [(NHART-1):0][(RETIRE-1):0];
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logic lrsc_cancel[(NHART-1):0][(RETIRE-1):0];
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assign clk = testbench.dut.clk;
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// assign InstrValidF = testbench.dut.core.ieu.InstrValidF; // not needed yet
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assign InstrValidD = testbench.dut.core.ieu.c.InstrValidD;
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assign InstrValidE = testbench.dut.core.ieu.c.InstrValidE;
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assign InstrValidM = testbench.dut.core.ieu.InstrValidM;
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assign InstrRawD = testbench.dut.core.ifu.InstrRawD;
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assign PCNextF = testbench.dut.core.ifu.PCNextF;
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assign PCF = testbench.dut.core.ifu.PCF;
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assign PCD = testbench.dut.core.ifu.PCD;
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assign PCE = testbench.dut.core.ifu.PCE;
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assign PCM = testbench.dut.core.ifu.PCM;
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assign reset = testbench.reset;
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assign StallE = testbench.dut.core.StallE;
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assign StallM = testbench.dut.core.StallM;
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assign StallW = testbench.dut.core.StallW;
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assign FlushD = testbench.dut.core.FlushD;
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assign FlushE = testbench.dut.core.FlushE;
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assign FlushM = testbench.dut.core.FlushM;
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assign FlushW = testbench.dut.core.FlushW;
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assign TrapM = testbench.dut.core.TrapM;
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assign HaltM = testbench.DCacheFlushStart;
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assign PrivilegeModeW = testbench.dut.core.priv.priv.privmode.PrivilegeModeW;
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assign STATUS_SXL = testbench.dut.core.priv.priv.csr.csrsr.STATUS_SXL;
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assign STATUS_UXL = testbench.dut.core.priv.priv.csr.csrsr.STATUS_UXL;
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always_comb begin
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// machine CSRs
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// *** missing PMP and performance counters.
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CSRArray[12'h300] = testbench.dut.core.priv.priv.csr.csrm.MSTATUS_REGW;
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CSRArray[12'h310] = testbench.dut.core.priv.priv.csr.csrm.MSTATUSH_REGW;
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CSRArray[12'h305] = testbench.dut.core.priv.priv.csr.csrm.MTVEC_REGW;
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CSRArray[12'h341] = testbench.dut.core.priv.priv.csr.csrm.MEPC_REGW;
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CSRArray[12'h306] = testbench.dut.core.priv.priv.csr.csrm.MCOUNTEREN_REGW;
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CSRArray[12'h320] = testbench.dut.core.priv.priv.csr.csrm.MCOUNTINHIBIT_REGW;
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CSRArray[12'h302] = testbench.dut.core.priv.priv.csr.csrm.MEDELEG_REGW;
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CSRArray[12'h303] = testbench.dut.core.priv.priv.csr.csrm.MIDELEG_REGW;
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CSRArray[12'h344] = testbench.dut.core.priv.priv.csr.csrm.MIP_REGW;
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CSRArray[12'h304] = testbench.dut.core.priv.priv.csr.csrm.MIE_REGW;
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CSRArray[12'h301] = testbench.dut.core.priv.priv.csr.csrm.MISA_REGW;
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CSRArray[12'hF14] = testbench.dut.core.priv.priv.csr.csrm.MHARTID_REGW;
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CSRArray[12'h340] = testbench.dut.core.priv.priv.csr.csrm.MSCRATCH_REGW;
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CSRArray[12'h342] = testbench.dut.core.priv.priv.csr.csrm.MCAUSE_REGW;
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CSRArray[12'h343] = testbench.dut.core.priv.priv.csr.csrm.MTVAL_REGW;
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CSRArray[12'hF11] = 0;
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CSRArray[12'hF12] = 0;
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CSRArray[12'hF13] = `XLEN'h100;
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CSRArray[12'hF15] = 0;
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CSRArray[12'h34A] = 0;
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// MCYCLE and MINSTRET
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CSRArray[12'hB00] = testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[0];
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CSRArray[12'hB02] = testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2];
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// supervisor CSRs
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CSRArray[12'h100] = testbench.dut.core.priv.priv.csr.csrs.SSTATUS_REGW;
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CSRArray[12'h104] = testbench.dut.core.priv.priv.csr.csrm.MIE_REGW & 12'h222;
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CSRArray[12'h105] = testbench.dut.core.priv.priv.csr.csrs.STVEC_REGW;
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CSRArray[12'h141] = testbench.dut.core.priv.priv.csr.csrs.SEPC_REGW;
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CSRArray[12'h106] = testbench.dut.core.priv.priv.csr.csrs.SCOUNTEREN_REGW;
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CSRArray[12'h180] = testbench.dut.core.priv.priv.csr.csrs.SATP_REGW;
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CSRArray[12'h140] = testbench.dut.core.priv.priv.csr.csrs.csrs.SSCRATCH_REGW;
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CSRArray[12'h143] = testbench.dut.core.priv.priv.csr.csrs.csrs.STVAL_REGW;
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CSRArray[12'h142] = testbench.dut.core.priv.priv.csr.csrs.csrs.SCAUSE_REGW;
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CSRArray[12'h144] = testbench.dut.core.priv.priv.csr.csrm.MIP_REGW & & 12'h222 & testbench.dut.core.priv.priv.csr.csrm.MIDELEG_REGW;
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// user CSRs
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CSRArray[12'h001] = testbench.dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW;
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CSRArray[12'h002] = testbench.dut.core.priv.priv.csr.csru.FRM_REGW;
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CSRArray[12'h003] = {testbench.dut.core.priv.priv.csr.csru.FRM_REGW, testbench.dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW};
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end
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genvar index;
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assign rf[0] = '0;
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for(index = 1; index < NUMREGS; index += 1)
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assign rf[index] = testbench.dut.core.ieu.dp.regf.rf[index];
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assign rf_a3 = testbench.dut.core.ieu.dp.regf.a3;
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assign rf_we3 = testbench.dut.core.ieu.dp.regf.we3;
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always_comb begin
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rf_wb <= '0;
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if(rf_we3)
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rf_wb[rf_a3] <= 1'b1;
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end
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for(index = 0; index < NUMREGS; index += 1)
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assign frf[index] = testbench.dut.core.fpu.fpu.fregfile.rf[index];
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assign frf_a4 = testbench.dut.core.fpu.fpu.fregfile.a4;
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assign frf_we4 = testbench.dut.core.fpu.fpu.fregfile.we4;
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always_comb begin
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frf_wb <= '0;
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if(frf_we4)
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frf_wb[frf_a4] <= 1'b1;
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end
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assign CSRAdrM = testbench.dut.core.priv.priv.csr.CSRAdrM;
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assign CSRWriteM = testbench.dut.core.priv.priv.csr.CSRWriteM;
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// pipeline to writeback stage
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flopenrc #(`XLEN) InstrRawEReg (clk, reset, FlushE, ~StallE, InstrRawD, InstrRawE);
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flopenrc #(`XLEN) InstrRawMReg (clk, reset, FlushM, ~StallM, InstrRawE, InstrRawM);
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flopenrc #(`XLEN) InstrRawWReg (clk, reset, FlushW, ~StallW, InstrRawM, InstrRawW);
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flopenrc #(`XLEN) PCWReg (clk, reset, FlushW, ~StallW, PCM, PCW);
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flopenrc #(1) InstrValidMReg (clk, reset, FlushW, ~StallW, InstrValidM, InstrValidW);
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flopenrc #(1) TrapWReg (clk, reset, 1'b0, ~StallW, TrapM, TrapW);
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flopenrc #(1) HaltWReg (clk, reset, 1'b0, ~StallW, HaltM, HaltW);
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flopenrc #(1) IntrFReg (clk, reset, 1'b0, ~StallF, TrapM, IntrF);
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flopenrc #(1) IntrDReg (clk, reset, FlushD, ~StallD, IntrF, IntrD);
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flopenrc #(1) IntrEReg (clk, reset, FlushE, ~StallE, IntrD, IntrE);
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flopenrc #(1) IntrMReg (clk, reset, FlushM, ~StallM, IntrE, IntrM);
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flopenrc #(1) IntrWReg (clk, reset, FlushW, ~StallW, IntrM, IntrW);
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flopenrc #(12) CSRAdrWReg (clk, reset, FlushW, ~StallW, CSRAdrM, CSRAdrW);
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flopenrc #(1) CSRWriteWReg (clk, reset, FlushW, ~StallW, CSRWriteM, CSRWriteW);
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// Initially connecting the writeback stage signals, but may need to use M stage
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// and gate on ~FlushW.
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assign valid = InstrValidW & ~StallW & ~FlushW;
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assign order[0][0] = CSRArray[12'hB02];
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assign insn[0][0] = InstrRawW;
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assign pc_rdata[0][0] = PCW;
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assign trap[0][0] = TrapW;
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assign halt[0][0] = HaltW;
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assign intr[0][0] = IntrW;
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assign mode[0][0] = PrivilegeModeW;
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assign ixl[0][0] = PrivilegeModeW == 2'b11 ? 2'b10 :
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PrivilegeModeW == 2'b01 ? STATUS_SXL : STATUS_UXL;
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assign pc_wdata[0][0] = ~FlushW ? PCM :
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~FlushM ? PCE :
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~FlushE ? PCD :
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~FlushD ? PCF : PCNextF;
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for(index = 0; index < `NUM_REGS; index += 1) begin
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assign x_wdata[0][0][index] = rf[index];
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assign x_wb[0][0][index] = rf_wb[index];
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assign f_wdata[0][0][index] = frf[index];
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assign f_wb[0][0][index] = frf_wb[index];
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end
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always_comb begin
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csr_wb[0][0] <= '0;
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if(CSRWriteW)
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csr_wb[0][0][CSRAdrW] <= 1'b1;
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end
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integer index3;
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always_comb begin
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for(index3 = 0; index3 < `NUM_CSRS; index3 += 1) begin
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if(CSRArray.exists(index3))
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csr[0][0][index3] = CSRArray[index3];
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else
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csr[0][0][index3] = '0;
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end
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end
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// *** implementation only cancel? so sc does not clear?
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assign lrsc_cancel[0][0] = '0;
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integer index2;
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always_ff @(posedge clk) begin
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if(valid) begin
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if(`PRINT_PC_INSTR & !(`PRINT_ALL | `PRINT_MOST))
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$display("order = %08d, PC = %08x, insn = %08x", order[0][0], pc_rdata[0][0], insn[0][0]);
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else if(`PRINT_MOST & !`PRINT_ALL)
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$display("order = %08d, PC = %010x, insn = %08x, trap = %1d, halt = %1d, intr = %1d, mode = %1x, ixl = %1x, pc_wdata = %010x, x%02d = %016x, f%02d = %016x, csr%03x = %016x",
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order[0][0], pc_rdata[0][0], insn[0][0], trap[0][0], halt[0][0], intr[0][0], mode[0][0], ixl[0][0], pc_wdata[0][0], rf_a3, x_wdata[0][0][rf_a3], frf_a4, f_wdata[0][0][frf_a4], CSRAdrW, csr[0][0][CSRAdrW]);
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else if(`PRINT_ALL) begin
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$display("order = %08d, PC = %08x, insn = %08x, trap = %1d, halt = %1d, intr = %1d, mode = %1x, ixl = %1x, pc_wdata = %08x",
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order[0][0], pc_rdata[0][0], insn[0][0], trap[0][0], halt[0][0], intr[0][0], mode[0][0], ixl[0][0], pc_wdata[0][0]);
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for(index2 = 0; index2 < `NUM_REGS; index2 += 1) begin
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$display("x%02d = %08x", index2, x_wdata[0][0][index2]);
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end
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for(index2 = 0; index2 < `NUM_REGS; index2 += 1) begin
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$display("f%02d = %08x", index2, f_wdata[0][0][index2]);
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end
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end
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end
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if(HaltW) $stop();
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end
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endmodule
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