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				https://github.com/openhwgroup/cvw
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			148 lines
		
	
	
		
			2.5 KiB
		
	
	
	
		
			ArmAsm
		
	
	
	
	
	
			
		
		
	
	
			148 lines
		
	
	
		
			2.5 KiB
		
	
	
	
		
			ArmAsm
		
	
	
	
	
	
.section .text
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.global enablePerfCnt
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.type enablePerfCnt, @function
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enablePerfCnt:
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	# a0 is the mask
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	csrrc x0, 0x320, a0 # clear bits to disable inhibit register
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	ret
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.section .text
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.global disablePerfCnt
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.type disablePerfCnt, @function
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disablePerfCnt:
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	# a0 is the mask
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	csrrs x0, 0x320, a0 # set bits to disable inhibit register
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	ret
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.section .text
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.global readPerfCnt
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.type readPerfCnt, @function
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readPerfCnt:
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	# a0 is the counter to read
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	# a1 is the flag to clear the register 
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	# return the value of the counter in a0
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	li t0, 0xB
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	# if the counter number is greater than the number
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	# of counters return a -1
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	bge a0, t0, readPerfCntError
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	# pointers are 8 bytes so shift a0 by 8
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	slli a0, a0, 3
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	li t1, 1
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	beq a1, t1, readPerfCntClear
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	la t0, csrTable
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	j skip
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readPerfCntClear:	
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	la t0, csrTable_clear	
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skip:	
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	add t0, t0, a0
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	ld t0, 0(t0)
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	jr t0
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csrCycle:
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	csrrs a0, 0xB00, x0
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	ret
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csrNull:
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	li a0, -1
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	ret
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csrInstrCount:
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	csrrs a0, 0xB02, x0
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	ret
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csrLoadStallCount:
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	csrrs a0, 0xB03, x0
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	ret
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csrBPWrongCount:
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	csrrs a0, 0xB04, x0
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	ret
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csrBPCount:
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	csrrs a0, 0xB05, x0
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	ret
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csrBTBWrongCount:
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	csrrs a0, 0xB06, x0
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	ret
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csrNonBRCFICount:
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	csrrs a0, 0xB07, x0
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	ret
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csrRasWrongCount:
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	csrrs a0, 0xB08, x0
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	ret
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csrReturnCount:
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	csrrs a0, 0xB09, x0
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	ret
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csrBTBClassWrongCount:
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	csrrs a0, 0xB0A, x0
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	ret
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csrCycle_clear:
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	csrrw a0, 0xB00, x0
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	ret
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csrNull_clear:
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	li a0, -1
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	ret
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csrInstrCount_clear:
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	csrrw a0, 0xB02, x0
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	ret
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csrLoadStallCount_clear:
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	csrrw a0, 0xB03, x0
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	ret
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csrBPWrongCount_clear:
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	csrrw a0, 0xB04, x0
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	ret
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csrBPCount_clear:
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	csrrw a0, 0xB05, x0
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	ret
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csrBTBWrongCount_clear:
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	csrrw a0, 0xB06, x0
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	ret
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csrNonBRCFICount_clear:
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	csrrw a0, 0xB07, x0
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	ret
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csrRasWrongCount_clear:
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	csrrw a0, 0xB08, x0
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	ret
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csrReturnCount_clear:
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	csrrw a0, 0xB09, x0
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	ret
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csrBTBClassWrongCount_clear:
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	csrrw a0, 0xB0A, x0
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	ret
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readPerfCntError:
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	li a0, -1
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	ret
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.section .data
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.align 3
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csrTable:	
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.8byte csrCycle			#0
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.8byte csrNull			#1
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.8byte csrInstrCount		#2
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.8byte csrLoadStallCount	#3
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.8byte csrBPWrongCount		#4
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.8byte csrBPCount		#5
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.8byte csrBTBWrongCount		#6
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.8byte csrNonBRCFICount		#7
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.8byte csrRasWrongCount		#8
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.8byte csrReturnCount		#9
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.8byte csrBTBClassWrongCount	#A
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csrTable_clear:	
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.8byte csrCycle_clear			#0
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.8byte csrNull_clear			#1
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.8byte csrInstrCount_clear		#2
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.8byte csrLoadStallCount_clear		#3
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.8byte csrBPWrongCount_clear		#4
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.8byte csrBPCount_clear			#5
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.8byte csrBTBWrongCount_clear		#6
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.8byte csrNonBRCFICount_clear		#7
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.8byte csrRasWrongCount_clear		#8
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.8byte csrReturnCount_clear		#9
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.8byte csrBTBClassWrongCount_clear	#A
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