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cvw/addins
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Rose Thompson a1c6bc854e Fixed a subtle questa sim bug with imperasDV. On some linux systems 
vsim will default to 32-bit mode rather than 64-bit, but the ImperasDV
libraries are 64-bit.  vsim must run in 64-bit mode.
2024-08-29 14:00:52 -07:00
..
ahbsdc@33418c8dc1 Replaced the git@github with hptts:github submodule for ahbsdc which I hope will fix Lee's clone issue 2023-12-11 14:12:38 -06:00
branch-predictor-simulator@3e424e902f Swap in branch predictor simulator handling compressed instruction offsets 2023-11-21 16:42:41 -08:00
coremark@f3e8f2e094 added back working coremark in benchmarks/riscv64-bcoremarkdirectory, experimental simplifications are in benchmarkscoremark/ but this doesn't currently work (some type of c bug) 2022-06-13 23:23:57 +00:00
cvw-arch-verif@9d54f3f8e9 Merge branch 'main' of github.com:openhwgroup/cvw 2024-08-21 16:24:10 -07:00
embench-iot@54fd9a0f10 repo cleanup and start to add CMO tests 2023-11-20 23:41:36 -08:00
FreeRTOS-Kernel@17a46c252f pulling in FreeRTOS/kernel Submodule 2023-06-13 10:41:18 -07:00
riscv-arch-test@7152865aca Update riscv-arch-test submodule 2024-06-18 23:34:02 -07:00
riscv-dv@f0c570d112 /cad/mentor/questa_sim-2023.4/questasim is fixed, relative paths to design and testbench files are fixed, and RISCV-DV submodule is updated back to the latest commit on master branch 2024-04-26 15:55:39 -07:00
riscvISACOV@ac9fa2d386 Fixed a subtle questa sim bug with imperasDV. On some linux systems 2024-08-29 14:00:52 -07:00
SoftFloat-3e Remove compiled softfloat binary 2024-08-15 19:01:13 -07:00
TestFloat-3e Moved Softfloat / TestFloat 2022-02-26 19:17:32 +00:00
verilog-ethernet@c180b22ed5 Updated verilog-ethernet to remove all verilator warnings or at least suppress them. 2024-07-24 10:13:03 -05:00
vivado-boards@e5f0728cd2 Added new submodule for digilent fpga boards. 2023-07-17 16:25:37 -05:00
README.md Added some documenation about sparse-checkout for verilog-ethernet submodule. 2024-07-19 13:11:48 -05:00
sparse-checkout Cleanup in prep to merge the rvvi branch into main. 2024-07-19 15:48:20 -05:00

README.md

verilog-ethernet contains many ethernet devices. Wally's synthesizable RVVI interface only requires a small subset of these files. To do a sparse checkout of this repo copy sparse-checkout to cvw/.git/modules/addins/verilog-ethernet/info This will make the working directory only contain the necessary files.