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54 lines
2.1 KiB
Systemverilog
54 lines
2.1 KiB
Systemverilog
///////////////////////////////////////////
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// sipo_generic_ce
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//
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// Written: Richard Davis
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// Modified: Ross Thompson September 20, 2021
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//
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// Purpose: serial to n-bit parallel shift register using register_ce.
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// When given a n-bit word as input transmit the message serially MSB (leftmost)
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// bit first.
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module sipo_generic_ce #(g_BUS_WIDTH)
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(input logic clk,
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input logic rst,
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input logic i_enable, // data valid, write to register
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input logic i_message_bit, // serial data
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output logic [g_BUS_WIDTH-1:0] o_data // message received, parallel data
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);
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logic [g_BUS_WIDTH-1:0] w_reg_d;
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logic [g_BUS_WIDTH-1:0] r_reg_q;
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flopenr #(g_BUS_WIDTH) shiftReg
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(.d(w_reg_d),
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.q(r_reg_q),
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.en(i_enable),
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.reset(rst),
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.clk(clk));
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assign w_reg_d = {r_reg_q[g_BUS_WIDTH-2:0], i_message_bit};
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assign o_data = r_reg_q;
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endmodule
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