mirror of
https://github.com/openhwgroup/cvw
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77 lines
3.3 KiB
Verilog
77 lines
3.3 KiB
Verilog
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module sd_top_wrapper #(parameter g_COUNT_WIDTH = 8)
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(
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input clk_in1_p,
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input clk_in1_n,
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input a_RST, // Reset signal (Must be held for minimum of 24 clock cycles)
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// a_RST MUST COME OUT OF RESET SYNCHRONIZED TO THE 1.2 GHZ CLOCK!
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// io_SD_CMD_z : inout std_logic; // SD CMD Bus
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inout SD_CMD, // CMD Response from card
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input [3:0] i_SD_DAT, // SD DAT Bus
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output o_SD_CLK, // SD CLK Bus
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// For communication with core cpu
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output o_READY_FOR_READ, // tells core that initialization sequence is completed and
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// sd card is ready to read a 512 byte block to the core.
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// Held high during idle until i_READ_REQUEST is received
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output o_SD_RESTARTING, // inform core the need to restart
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input i_READ_REQUEST, // After Ready for read is sent to the core, the core will
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// pulse this bit high to indicate it wants the block at this address
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output [3:0] o_DATA_TO_CORE, // nibble being sent to core when DATA block is
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// being published
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output o_DATA_VALID // held high while data being read to core to indicate that it is valid
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);
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wire CLK;
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wire LIMIT_SD_TIMERS;
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wire [g_COUNT_WIDTH-1:0] i_COUNT_IN_MAX;
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wire [4095:0] ReadData; // full 512 bytes to Bus
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wire [32:9] i_BLOCK_ADDR; // see "Addressing" in parts.fods (only 8GB total capacity is used)
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wire o_SD_CMD; // CMD Command from host
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wire i_SD_CMD; // CMD Command from host
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wire o_SD_CMD_OE; // Direction of SD_CMD
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wire [2:0] o_ERROR_CODE_Q; // indicates which error occured
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wire o_FATAL_ERROR; // indicates that the FATAL ERROR register has updated
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wire o_LAST_NIBBLE; // pulse when last nibble is sent
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assign LIMIT_SD_TIMERS = 1'b0;
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assign i_COUNT_IN_MAX = -8'd62;
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assign i_BLOCK_ADDR = 23'h0;
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clk_wiz_0 clk_wiz_0(.clk_in1_p(clk_in1_p),
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.clk_in1_n(clk_in1_n),
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.reset(1'b0),
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.clk_out1(CLK),
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.locked(locked));
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IOBUF SDCMDIODriver(.T(~o_SD_CMD_OE),
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.I(o_SD_CMD),
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.O(i_SD_CMD),
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.IO(SD_CMD));
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sd_top #(g_COUNT_WIDTH)
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sd_top(.CLK(CLK),
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.a_RST(a_RST),
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.i_SD_CMD(i_SD_CMD), // CMD Response from card
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.o_SD_CMD(o_SD_CMD), // CMD Command from host
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.o_SD_CMD_OE(o_SD_CMD_OE), // Direction of SD_CMD
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.i_SD_DAT(i_SD_DAT), // SD DAT Bus
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.o_SD_CLK(o_SD_CLK), // SD CLK Bus
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.i_BLOCK_ADDR(i_BLOCK_ADDR), // see "Addressing" in parts.fods (only 8GB total capacity is used)
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.o_READY_FOR_READ(o_READY_FOR_READ), // tells core that initialization sequence is completed and
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.o_SD_RESTARTING(o_SD_RESTARTING), // inform core the need to restart
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.i_READ_REQUEST(i_READ_REQUEST), // After Ready for read is sent to the core, the core will
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.o_DATA_TO_CORE(o_DATA_TO_CORE), // nibble being sent to core when DATA block is
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.ReadData(ReadData), // full 512 bytes to Bus
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.o_DATA_VALID(o_DATA_VALID), // held high while data being read to core to indicate that it is valid
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.o_LAST_NIBBLE(o_LAST_NIBBLE), // pulse when last nibble is sent
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.o_ERROR_CODE_Q(o_ERROR_CODE_Q), // indicates which error occured
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.o_FATAL_ERROR(o_FATAL_ERROR), // indicates that the FATAL ERROR register has updated
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.i_COUNT_IN_MAX(i_COUNT_IN_MAX),
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.LIMIT_SD_TIMERS(LIMIT_SD_TIMERS)
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);
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endmodule
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